Hello all
Since the make 3.81 release in Cygwin, I constantly have issues with
this released version:
When using Mentor ModelSim to compile and simulate VHDL, the released
make 3.81 fails by executing generated Makefiles from ModelSim (using
'vmake > Makefile').
It does not occur with make 3.79.1 or the patched 3.81 version available
at https://software.sandia.gov/trac/acro/ticket/2835 and using the
binary at http://www.cmake.org/files/cygwin/make.exe
Command line log:
-----------------
ad...@blueshark /cygdrive/d/Xilinx/example_design/sim
$ make
Makefile:128: *** multiple target patterns. Stop.
ad...@blueshark /cygdrive/d/Xilinx/example_design/sim
$ make_3.79.1.exe
make_3.79.1: Nothing to be done for `whole_library'.
ad...@blueshark /cygdrive/d/Xilinx/example_design/sim
$ make_3.81_fixed.exe
make_3.81_fixed: Nothing to be done for `whole_library'.
If you could fix this when time comes by, I think many hardware
engineers will be very happy...
The last discussion about this issue was in 2006 at
http://sourceware.org/ml/cygwin/2006-07/msg00667.html
Attached as well the (generated) Makefile, where the released Cygwin
make 3.81 complains about line 128
Many thanks!
Peter
# Generated by vmake version 2.2
# Define path to each library
LIB_UNISIM = D:/Libraries/ISE/unisim/
LIB_IEEE = c:\Tools\HW\ModelSim\win32/../ieee
LIB_WORK = work
# Define path to each design unit
IEEE__numeric_std = $(LIB_IEEE)/numeric_std/_primary.dat
UNISIM__vcomponents = $(LIB_UNISIM)/vcomponents/_primary.dat
IEEE__std_logic_1164 = $(LIB_IEEE)/std_logic_1164/_primary.dat
WORK__wiredelay__wiredelay_a = $(LIB_WORK)/wiredelay/wiredelay_a.dat
WORK__wiredelay = $(LIB_WORK)/wiredelay/_primary.dat
WORK__sim_tb_top__arch = $(LIB_WORK)/sim_tb_top/arch.dat
WORK__sim_tb_top = $(LIB_WORK)/sim_tb_top/_primary.dat
WORK__glbl = $(LIB_WORK)/glbl/_primary.dat
WORK__ddr2_usr_wr__syn = $(LIB_WORK)/ddr2_usr_wr/syn.dat
WORK__ddr2_usr_wr = $(LIB_WORK)/ddr2_usr_wr/_primary.dat
WORK__ddr2_usr_top__syn = $(LIB_WORK)/ddr2_usr_top/syn.dat
WORK__ddr2_usr_top = $(LIB_WORK)/ddr2_usr_top/_primary.dat
WORK__ddr2_usr_rd__syn = $(LIB_WORK)/ddr2_usr_rd/syn.dat
WORK__ddr2_usr_rd = $(LIB_WORK)/ddr2_usr_rd/_primary.dat
WORK__ddr2_usr_addr_fifo__syn = $(LIB_WORK)/ddr2_usr_addr_fifo/syn.dat
WORK__ddr2_usr_addr_fifo = $(LIB_WORK)/ddr2_usr_addr_fifo/_primary.dat
WORK__ddr2_top__syn = $(LIB_WORK)/ddr2_top/syn.dat
WORK__ddr2_top = $(LIB_WORK)/ddr2_top/_primary.dat
WORK__ddr2_tb_top__syn = $(LIB_WORK)/ddr2_tb_top/syn.dat
WORK__ddr2_tb_top = $(LIB_WORK)/ddr2_tb_top/_primary.dat
WORK__ddr2_tb_test_gen__syn = $(LIB_WORK)/ddr2_tb_test_gen/syn.dat
WORK__ddr2_tb_test_gen = $(LIB_WORK)/ddr2_tb_test_gen/_primary.dat
WORK__ddr2_tb_test_data_gen__syn = $(LIB_WORK)/ddr2_tb_test_data_gen/syn.dat
WORK__ddr2_tb_test_data_gen = $(LIB_WORK)/ddr2_tb_test_data_gen/_primary.dat
WORK__ddr2_tb_test_cmp__syn = $(LIB_WORK)/ddr2_tb_test_cmp/syn.dat
WORK__ddr2_tb_test_cmp = $(LIB_WORK)/ddr2_tb_test_cmp/_primary.dat
WORK__ddr2_tb_test_addr_gen__syn = $(LIB_WORK)/ddr2_tb_test_addr_gen/syn.dat
WORK__ddr2_tb_test_addr_gen = $(LIB_WORK)/ddr2_tb_test_addr_gen/_primary.dat
WORK__ddr2_sdram__arc_mem_interface_top =
$(LIB_WORK)/ddr2_sdram/arc_mem_interface_top.dat
WORK__ddr2_sdram = $(LIB_WORK)/ddr2_sdram/_primary.dat
WORK__ddr2_phy_write__syn = $(LIB_WORK)/ddr2_phy_write/syn.dat
WORK__ddr2_phy_write = $(LIB_WORK)/ddr2_phy_write/_primary.dat
WORK__ddr2_phy_top__syn = $(LIB_WORK)/ddr2_phy_top/syn.dat
WORK__ddr2_phy_top = $(LIB_WORK)/ddr2_phy_top/_primary.dat
WORK__ddr2_phy_io__syn = $(LIB_WORK)/ddr2_phy_io/syn.dat
WORK__ddr2_phy_io = $(LIB_WORK)/ddr2_phy_io/_primary.dat
WORK__ddr2_phy_init__syn = $(LIB_WORK)/ddr2_phy_init/syn.dat
WORK__ddr2_phy_init = $(LIB_WORK)/ddr2_phy_init/_primary.dat
WORK__ddr2_phy_dqs_iob__syn = $(LIB_WORK)/ddr2_phy_dqs_iob/syn.dat
WORK__ddr2_phy_dqs_iob = $(LIB_WORK)/ddr2_phy_dqs_iob/_primary.dat
WORK__ddr2_phy_dq_iob__syn = $(LIB_WORK)/ddr2_phy_dq_iob/syn.dat
WORK__ddr2_phy_dq_iob = $(LIB_WORK)/ddr2_phy_dq_iob/_primary.dat
WORK__ddr2_phy_dm_iob__syn = $(LIB_WORK)/ddr2_phy_dm_iob/syn.dat
WORK__ddr2_phy_dm_iob = $(LIB_WORK)/ddr2_phy_dm_iob/_primary.dat
WORK__ddr2_phy_ctl_io__syn = $(LIB_WORK)/ddr2_phy_ctl_io/syn.dat
WORK__ddr2_phy_ctl_io = $(LIB_WORK)/ddr2_phy_ctl_io/_primary.dat
WORK__ddr2_phy_calib__syn = $(LIB_WORK)/ddr2_phy_calib/syn.dat
WORK__ddr2_phy_calib = $(LIB_WORK)/ddr2_phy_calib/_primary.dat
WORK__ddr2_model = $(LIB_WORK)/ddr2_model/_primary.dat
WORK__ddr2_mem_if_top__syn = $(LIB_WORK)/ddr2_mem_if_top/syn.dat
WORK__ddr2_mem_if_top = $(LIB_WORK)/ddr2_mem_if_top/_primary.dat
WORK__ddr2_infrastructure__syn = $(LIB_WORK)/ddr2_infrastructure/syn.dat
WORK__ddr2_infrastructure = $(LIB_WORK)/ddr2_infrastructure/_primary.dat
WORK__ddr2_idelay_ctrl__syn = $(LIB_WORK)/ddr2_idelay_ctrl/syn.dat
WORK__ddr2_idelay_ctrl = $(LIB_WORK)/ddr2_idelay_ctrl/_primary.dat
WORK__ddr2_ctrl__syn = $(LIB_WORK)/ddr2_ctrl/syn.dat
WORK__ddr2_ctrl = $(LIB_WORK)/ddr2_ctrl/_primary.dat
WORK__ddr2_chipscope = $(LIB_WORK)/ddr2_chipscope/_primary.dat
VCOM = vcom
VLOG = vlog
VOPT = vopt
SCCOM = sccom
whole_library : $(WORK__wiredelay__wiredelay_a) \
$(WORK__wiredelay) \
$(WORK__sim_tb_top__arch) \
$(WORK__sim_tb_top) \
$(WORK__glbl) \
$(WORK__ddr2_usr_wr__syn) \
$(WORK__ddr2_usr_wr) \
$(WORK__ddr2_usr_top__syn) \
$(WORK__ddr2_usr_top) \
$(WORK__ddr2_usr_rd__syn) \
$(WORK__ddr2_usr_rd) \
$(WORK__ddr2_usr_addr_fifo__syn) \
$(WORK__ddr2_usr_addr_fifo) \
$(WORK__ddr2_top__syn) \
$(WORK__ddr2_top) \
$(WORK__ddr2_tb_top__syn) \
$(WORK__ddr2_tb_top) \
$(WORK__ddr2_tb_test_gen__syn) \
$(WORK__ddr2_tb_test_gen) \
$(WORK__ddr2_tb_test_data_gen__syn) \
$(WORK__ddr2_tb_test_data_gen) \
$(WORK__ddr2_tb_test_cmp__syn) \
$(WORK__ddr2_tb_test_cmp) \
$(WORK__ddr2_tb_test_addr_gen__syn) \
$(WORK__ddr2_tb_test_addr_gen) \
$(WORK__ddr2_sdram__arc_mem_interface_top) \
$(WORK__ddr2_sdram) \
$(WORK__ddr2_phy_write__syn) \
$(WORK__ddr2_phy_write) \
$(WORK__ddr2_phy_top__syn) \
$(WORK__ddr2_phy_top) \
$(WORK__ddr2_phy_io__syn) \
$(WORK__ddr2_phy_io) \
$(WORK__ddr2_phy_init__syn) \
$(WORK__ddr2_phy_init) \
$(WORK__ddr2_phy_dqs_iob__syn) \
$(WORK__ddr2_phy_dqs_iob) \
$(WORK__ddr2_phy_dq_iob__syn) \
$(WORK__ddr2_phy_dq_iob) \
$(WORK__ddr2_phy_dm_iob__syn) \
$(WORK__ddr2_phy_dm_iob) \
$(WORK__ddr2_phy_ctl_io__syn) \
$(WORK__ddr2_phy_ctl_io) \
$(WORK__ddr2_phy_calib__syn) \
$(WORK__ddr2_phy_calib) \
$(WORK__ddr2_model) \
$(WORK__ddr2_mem_if_top__syn) \
$(WORK__ddr2_mem_if_top) \
$(WORK__ddr2_infrastructure__syn) \
$(WORK__ddr2_infrastructure) \
$(WORK__ddr2_idelay_ctrl__syn) \
$(WORK__ddr2_idelay_ctrl) \
$(WORK__ddr2_ctrl__syn) \
$(WORK__ddr2_ctrl) \
$(WORK__ddr2_chipscope)
$(WORK__ddr2_chipscope) : ../rtl/ddr2_chipscope.vhd \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_chipscope.vhd
$(WORK__ddr2_ctrl) \
$(WORK__ddr2_ctrl__syn) : ../rtl/ddr2_ctrl.vhd \
$(IEEE__numeric_std) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_ctrl.vhd
$(WORK__ddr2_idelay_ctrl) \
$(WORK__ddr2_idelay_ctrl__syn) : ../rtl/ddr2_idelay_ctrl.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_idelay_ctrl.vhd
$(WORK__ddr2_infrastructure) \
$(WORK__ddr2_infrastructure__syn) : ../rtl/ddr2_infrastructure.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_infrastructure.vhd
$(WORK__ddr2_mem_if_top) \
$(WORK__ddr2_mem_if_top__syn) : ../rtl/ddr2_mem_if_top.vhd \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_mem_if_top.vhd
$(WORK__ddr2_model) : ddr2_model.v ddr2_model_parameters.vh
$(VLOG) +incdir+. +define+x512Mb +define+sg3 \
+define+x16 -L mtiAvm -L mtiOvm -L mtiUPF \
ddr2_model.v
$(WORK__ddr2_phy_calib) \
$(WORK__ddr2_phy_calib__syn) : ../rtl/ddr2_phy_calib.vhd \
$(UNISIM__vcomponents) \
$(IEEE__numeric_std) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_phy_calib.vhd
$(WORK__ddr2_phy_ctl_io) \
$(WORK__ddr2_phy_ctl_io__syn) : ../rtl/ddr2_phy_ctl_io.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_phy_ctl_io.vhd
$(WORK__ddr2_phy_dm_iob) \
$(WORK__ddr2_phy_dm_iob__syn) : ../rtl/ddr2_phy_dm_iob.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_phy_dm_iob.vhd
$(WORK__ddr2_phy_dq_iob) \
$(WORK__ddr2_phy_dq_iob__syn) : ../rtl/ddr2_phy_dq_iob.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_phy_dq_iob.vhd
$(WORK__ddr2_phy_dqs_iob) \
$(WORK__ddr2_phy_dqs_iob__syn) : ../rtl/ddr2_phy_dqs_iob.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_phy_dqs_iob.vhd
$(WORK__ddr2_phy_init) \
$(WORK__ddr2_phy_init__syn) : ../rtl/ddr2_phy_init.vhd \
$(UNISIM__vcomponents) \
$(IEEE__numeric_std) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_phy_init.vhd
$(WORK__ddr2_phy_io) \
$(WORK__ddr2_phy_io__syn) : ../rtl/ddr2_phy_io.vhd \
$(UNISIM__vcomponents) \
$(IEEE__numeric_std) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_phy_io.vhd
$(WORK__ddr2_phy_top) \
$(WORK__ddr2_phy_top__syn) : ../rtl/ddr2_phy_top.vhd \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_phy_top.vhd
$(WORK__ddr2_phy_write) \
$(WORK__ddr2_phy_write__syn) : ../rtl/ddr2_phy_write.vhd \
$(IEEE__numeric_std) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_phy_write.vhd
$(WORK__ddr2_sdram) \
$(WORK__ddr2_sdram__arc_mem_interface_top) : ../rtl/ddr2_sdram.vhd \
$(WORK__ddr2_chipscope) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_sdram.vhd
$(WORK__ddr2_tb_test_addr_gen) \
$(WORK__ddr2_tb_test_addr_gen__syn) : ../rtl/ddr2_tb_test_addr_gen.vhd \
$(UNISIM__vcomponents) \
$(IEEE__numeric_std) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_tb_test_addr_gen.vhd
$(WORK__ddr2_tb_test_cmp) \
$(WORK__ddr2_tb_test_cmp__syn) : ../rtl/ddr2_tb_test_cmp.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_tb_test_cmp.vhd
$(WORK__ddr2_tb_test_data_gen) \
$(WORK__ddr2_tb_test_data_gen__syn) : ../rtl/ddr2_tb_test_data_gen.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_tb_test_data_gen.vhd
$(WORK__ddr2_tb_test_gen) \
$(WORK__ddr2_tb_test_gen__syn) : ../rtl/ddr2_tb_test_gen.vhd \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_tb_test_gen.vhd
$(WORK__ddr2_tb_top) \
$(WORK__ddr2_tb_top__syn) : ../rtl/ddr2_tb_top.vhd \
$(UNISIM__vcomponents) \
$(IEEE__numeric_std) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_tb_top.vhd
$(WORK__ddr2_top) \
$(WORK__ddr2_top__syn) : ../rtl/ddr2_top.vhd \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_top.vhd
$(WORK__ddr2_usr_addr_fifo) \
$(WORK__ddr2_usr_addr_fifo__syn) : ../rtl/ddr2_usr_addr_fifo.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_usr_addr_fifo.vhd
$(WORK__ddr2_usr_rd) \
$(WORK__ddr2_usr_rd__syn) : ../rtl/ddr2_usr_rd.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_usr_rd.vhd
$(WORK__ddr2_usr_top) \
$(WORK__ddr2_usr_top__syn) : ../rtl/ddr2_usr_top.vhd \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_usr_top.vhd
$(WORK__ddr2_usr_wr) \
$(WORK__ddr2_usr_wr__syn) : ../rtl/ddr2_usr_wr.vhd \
$(UNISIM__vcomponents) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../rtl/ddr2_usr_wr.vhd
$(WORK__glbl) : ../sim/glbl.v
$(VLOG) -L mtiAvm -L mtiOvm -L mtiUPF \
../sim/glbl.v
$(WORK__sim_tb_top) \
$(WORK__sim_tb_top__arch) : ../sim/sim_tb_top.vhd \
$(UNISIM__vcomponents) \
$(IEEE__numeric_std) \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../sim/sim_tb_top.vhd
$(WORK__wiredelay) \
$(WORK__wiredelay__wiredelay_a) : ../sim/wiredly.vhd \
$(IEEE__std_logic_1164)
$(VCOM) -2002 ../sim/wiredly.vhd
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