jk> Intel CPUs with family 0x6, model 0xE and later (i.e., Intel Core(TM)) jk> have a PMC architecture that differs somewhat from previous CPUs in jk> family 0x6. Even though the basic programming model is similar, the jk> documented set of legal values that may be loaded into their PMC MSRs jk> differs from that of the previous PMCs in family 0x6 and reusing bit jk> values valid for the older PMCs could result in undefined behaviour in jk> the general case.
kk> What is your expected timeline for fixing this and the other missing CPU kk> family support (Intel Woodcrest, etc)? It is on my list of things to do, after callchain capture support is folded into CVS and stabilized. kk> It's a serious limitation to not be able to run hwpmc on modern kk> CPUs, and I argue that a partial implementation is much better kk> than no implementation. The problem is that our 'partial implementation' isn't quite correct. At the time ps@ committed rev 1.4, the processor was unreleased and documentation was not available, and our guess was that the PMCs in the new CPU would be compatible with earlier CPUs. Unfortunately the PMCs aren't totally backward compatible. These compatibility issues may not affect a user who wants to run `pmcstat -S instructions' on a single Core CPU (the common case perhaps) since the alias name `instructions' translates to a P6 PMC event selector that happens to select the same hardware event on a Core PMC. However, users specifying other kinds of P6 PMC events run the risk of measuring garbage and thus being lead on a wild goose chase. So I'd rather not claim that hwpmc can support a PMC family when it actually can't do it correctly. Regards, Koshy <[EMAIL PROTECTED]> _______________________________________________ cvs-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/cvs-all To unsubscribe, send any mail to "[EMAIL PROTECTED]"
