All, A use case for the title is beginning to emerge for a number of Asus P8x7x boards. For example: https://review.coreboot.org/c/coreboot/+/85413 and https://review.coreboot.org/c/coreboot/+/85768
Many standard ATX boards in the family have more peripherals than the 8 PCIe lanes available out of the PCH, so some are structured to share 3 of the 4 PCIe lanes originally earmarked for an x4 slot. They do this with a number of 2-way PCIe switches (specifically ASM1440 - no datasheet, but I figured out the pinout, only thing I don't know is the polarity of the control signal) controlled by GPIOs either on the super I/O or the PCH. With vendor firmware this is an option that can be configured from UEFI setup itself. I can handle GPIOs fine, but stealing lanes from an x4 slot requires changing a soft strap to reconfigure lanes 1-4 from one x4 port to four x1 ports. The only strategy I can see work is flash a modified soft strap to the descriptor, during bootblock before PCI bus scan happens and before SPI is locked down, trigger a full platform reset (eg. outb(0xe, 0xcf9)) , then program the GPIOs to match the updated soft strap. Has this been done before in coreboot so there is code I can lift? Thanks Keith _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
