Hi, I am trying to understand how cache as ram works and how coreboot implements it. I am looking into this piece of code: https://github.com/coreboot/coreboot/blob/main/src/soc/intel/common/block/cpu/car/cache_as_ram.S#L53C1-L60C11 and if I try to summarize the whole process of setting up cache as ram is that after setting up MTRR for the region as write-back, we need to enable cache, invalidate the cache, call "clear_car" so that the cachelines are marked for these memory addresses. I understand that this is necessary so that later when CR0.CD = 1, CR0.NW = 1 is done, the memory accesses to these locations will cause cache hits and if written to these memory locations, the write-back policy will cause only the cache to be updated.
My question is when "clear_car" is executed, wouldn't it cause the cache lines to be filled first (as it's a cache miss), by the cpu doing memory accesses by trying to "read" those locations? But DRAM isn't initialized still, so does that mean that the cache lines will be filled with garbage and this is okay, right? And then the cache is updated with some value with the stosl instruction. I am just not sure about if the cache lines will be filled with garbage when the cpu will first fill up the cache lines by trying to read those memory locations as there is no DRAM initialized. It would be great if someone could help me to understand this process. Thanks! Regards, Dorjoy _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
