Dear Moorthi,
Welcome to coreboot.
Am 31.07.24 um 07:45 schrieb Moorthi M.s:
I am developing coreboot (ver 4.17) along with UEFI payload for a custom
board derived from CFL H RVP11 CRB.
I included the CACHE_MRC_SETTINGS to reduce the boot time on subsequent
power on.
But the time was not reducing and on every power on, around 18 seconds are
taking between post code 0x92 (Ram Init) and 0x98 (Ram Init Exit). And
always prints as " MRC: cache data 'RW_MRC_CACHE' needs update".
Because of this coreboot takes around 45 secs to boot.
Why every time the MRC cache data is changing? Why the processor is not
using the MRC cached data?
Without knowing the code you are using, nobody knows. Did you dump the
cache data to compare?
Is there any other configurations needs to be done?
Unfortunately, you did not provide enough information to answer your
question. Please provide at least your configuration and the verbose
logs. Best would be to upload your code (and the schematics).
Also, why do you use coreboot 4.17? 24.05 is the latest release.
Kind regards,
Paul
PS: Just to mention it, there are coreboot consultants [1], that might
save you some time in the end.
[1]: https://coreboot.org/consulting.html
_______________________________________________
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org
