On 5/21/21, Arthur Heymans <art...@aheymans.xyz> wrote: > Hi > > Thanks for sharing your findings. THe flash is 256K big, which is quite > small these days. > When building coreboot with default settings but without a payload I find > that there is 69K empty space left for payloads. > > Some future developments I have been working on might give a bit more > breathing space. > - I want to make romstage optional and include the sources in the > bootblock: That should shave off roughly 10K of romstage. > - I have compressing postcar working (maybe you can also disable the > postcar console to reduce size). That's also 2-3k size gains > at likely the const of a tiny bit of boot performance on this platform. > - I also have some WIP code to merge postcar into ramstage which would save > 15k. > > Maybe on coreboot release 4.15 you will have a better time building a fully > working image with the default configuration. > > Kind regards > > Arthur Heymans >
I didn't realize there was development going on to save rom space, that's good to know. I should really be looking at more of the changes going on. > On Fri, May 21, 2021 at 7:08 AM Paul Menzel <pmen...@molgen.mpg.de> wrote: > >> Dear Branden, >> >> >> Am 21.05.21 um 05:36 schrieb Branden Waldner: >> > When testing the latest coreboot code before the 4.14 release, I found >> > I couldn't build a working image with the default (or what I usually >> > use) config for the asus/p2b. I figured out that it failed to build >> > with an error of not enough space in cbfs after the merge to enable >> > bootblock console for intel 440bx. >> > Following this, I just disabled microcode firmware to free up space >> > and it worked fine, even without the microcode update. Specifically >> > selecting the microcode for the cpu I'm using would probably be better >> > though. >> > I'm just commenting on my findings, not really expecting anything. I >> > had intended on trying to obtain some larger flash chips yet, though I >> > never got around to it. It would still leave a broken default build >> > config though with the standard rom size. >> >> Thank you for sharing your findings. All default configurations are >> tested – without a payload though I believe –, so please attach your >> configuration, `defconfig` created by `make savedefconfig`, and your >> payload and size. >> >> >> Kind regards, >> >> Paul I just did a make distclean and selected vendor asus and board p2b, which doesn't make for much of a defconfig to show. I've just been using seabios as the default/only payload, partly because that's all it needs to work and partly because there was no space for anything else before anyways. Thanks for the replies, Branden _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
