Hello Michail setting the register values for PCICLOCK to 25MHz as on the Braswell protectli devices did the trick for me, i have serial working now flawlessly. Did you see the git diff i send ?
I have trouble get superiotool to detect the SUPERIO chip it seems the current version is not even probing for the 8613E. here is the cpuinfo ( i disabled SMT and SGX in coreboot) Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian Address sizes: 39 bits physical, 48 bits virtual CPU(s): 2 On-line CPU(s) list: 0,1 Thread(s) per core: 1 Core(s) per socket: 2 Socket(s): 1 NUMA node(s): 1 Vendor ID: GenuineIntel CPU family: 6 Model: 142 Model name: Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz Stepping: 9 CPU MHz: 1100.126 CPU max MHz: 3100.0000 CPU min MHz: 400.0000 BogoMIPS: 5424.00 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 256K L3 cache: 3072K NUMA node0 CPU(s): 0,1 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp md_clear flush_l1d On Friday, May 14, 2021 11:30 CEST, Michał Żygowski <michal.zygow...@3mdeb.com> wrote: Iain, Also please check what is the CPU on your platform. Please run `cat /proc/cpuinfo` and paste me the CPU brand string, because FW6 has refreshed variants based on Kaby Lake Refresh CPUs and different Super I/O ITE8613, which we will upload the source code to upstream coreboot soon. On 5/13/21 8:15 PM, lain wrote: > Hello Michal, > i found the regarding problem. > The board i got from aliexpress has an SUPERIO 8613 insteat of a > SUPERIO 8772F, this other superio seem to be support by coreboot but > dumbly changing this in the .config seems to fail, do you think you > could help me compiling it for this SUPERIO chip ? > > best regards > lain Best regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com
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