Hi everyone,
I have a motherboard (Supermicro X10SL7-F) that appears to be very similar to
the supported board X10SLM+-F
I would like comment on whether anyone thinks running coreboot on this board
would be possible!
And if so what work would need to be done to make it a reality.
1.
Board description:
Vendor: Supermicro
Board name: X10SL7-F
CPU: Intel Xeon E3-1231 v3 (Haswell)
Northbridge: ?
Southbridge: Intel C222 Express PCH
This board also contains a built-in LSI 2308 disk controller providing
8 SAS2 ports
2.
Output of lspci -tvnn on Ubuntu Server 18.04.5:
-[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3 Processor DRAM Controller
[8086:0c08]
+-01.0-[01]--
+-01.1-[02]----00.0 LSI Logic / Symbios Logic SAS2308 PCI-Express
Fusion-MPT SAS-2 [1000:0086]
+-14.0 Intel Corporation 8 Series/C220 Series Chipset Family USB
xHCI [8086:8c31]
+-1a.0 Intel Corporation 8 Series/C220 Series Chipset Family USB
EHCI #2 [8086:8c2d]
+-1c.0-[03-04]----00.0-[04]----00.0 ASPEED Technology, Inc. ASPEED
Graphics Family [1a03:2000]
+-1c.2-[05]----00.0 Intel Corporation I210 Gigabit Network
Connection [8086:1533]
+-1c.3-[06]----00.0 Intel Corporation I210 Gigabit Network
Connection [8086:1533]
+-1d.0 Intel Corporation 8 Series/C220 Series Chipset Family USB
EHCI #1 [8086:8c26]
+-1f.0 Intel Corporation C222 Series Chipset Family Server
Essential SKU LPC Controller [8086:8c52]
+-1f.2 Intel Corporation 8 Series/C220 Series Chipset Family 6-port
SATA Controller 1 [AHCI mode] [8086:8c02]
+-1f.3 Intel Corporation 8 Series/C220 Series Chipset Family SMBus
Controller [8086:8c22]
\-1f.6 Intel Corporation 8 Series Chipset Family Thermal Management
Controller [8086:8c24]
3.
Output of superiotool -dV on Ubuntu Server 18.04.5:
superiotool r6637
Probing for Nuvoton Super I/O at 0x2e...
Found Nuvoton NCT6776F (C) (id=0xc333) at 0x2e
Register dump:
idx 10 11 13 14 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 2a
2b 2c 2d 2e 2f
val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff
def ff ff 00 00 ff ff ff ff f0 78 00 00 ff ff c3 33 ff 00 64 00 MM 00 00 c0
00 81 00 00 MM
LDN 0x00 (FDC)
idx 30 60 61 70 74 f0 f1 f2 f4 f5
val ff ff ff ff ff ff ff ff ff ff
def 01 03 f0 06 02 0e 00 ff 00 00
LDN 0x01 (Parallel Port)
idx 30 60 61 70 74 f0
val ff ff ff ff ff ff
def 01 03 78 07 04 3f
LDN 0x02 (UART A)
idx 30 60 61 70 f0 f2
val ff ff ff ff ff ff
def 01 03 f8 04 00 00
LDN 0x03 (UART B, IR)
idx 30 60 61 70 f0 f1 f2
val ff ff ff ff ff ff ff
def 01 02 f8 03 00 00 00
LDN 0x05 (Keyboard Controller)
idx 30 60 61 62 63 70 72 f0
val ff ff ff ff ff ff ff ff
def 00 00 00 00 00 00 00 83
LDN 0x06 (CIR)
idx 30 60 61 70 f0 f1 f2 f3
val ff ff ff ff ff ff ff ff
def 00 00 00 00 08 09 32 00
LDN 0x07 (GPIO6, GPIO7, GPIO8, GPIO9)
idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee f4 f5 f6 f7 f8
val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
def 03 ff 00 00 00 ef 00 00 00 ff 00 00 00 00 00 00 ff 00 00 00 00
LDN 0x08 (WDT1, GPIO0, GPIO1, GPIOA)
idx 30 60 61 e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7
val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
def 02 00 00 ff 00 00 00 ef ff 00 00 00 00 00 00 00
LDN 0x09 (GPIO2, GPIO3, GPIO4, GPIO5)
idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ee f0 f1 f2 f4 f5 f6 f7 fe
val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
def 04 df 00 00 00 ff 00 00 00 00 00 00 00 00 ff 00 00 ff 00 00 00 00
LDN 0x0a (ACPI)
idx e0 e1 e2 e3 e4 e5 e6 e7 e9 ee f0 f2 f3 f4 f6 f7 fe
val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
def 01 00 00 00 00 02 1c 00 00 00 00 00 00 00 00 c0 00
LDN 0x0b (Hardware Monitor, Front Panel LED)
idx 30 60 61 62 63 70 e0 e1 e2 f0 f1 f2 f5 f6 f7 f8 f9 fa
val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
def 00 00 00 00 00 00 7f 7f ff 00 00 00 10 00 87 47 00 00
LDN 0x0d (VID)
idx e0 e1 e2 e3 e4 e5 e6 e9 ee ef f0 f4 f5
val ff ff ff ff ff ff ff ff ff ff ff ff ff
def 00 00 00 00 00 00 00 00 88 00 00 00 00
LDN 0x0e (CIR WAKE-UP)
idx 30 60 61 70
val ff ff ff ff
def 00 00 00 00
LDN 0x0f (GPIO Push-Pull or Open-drain)
idx e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2
val ff ff ff ff ff ff ff ff ff ff ff ff ff
def ff df ff fe f6 ff ff d3 ff 9f 00 00 00
LDN 0x14 (SVID)
idx e0 e1 e3 e4
val ff ff ff ff
def 00 80 00 00
LDN 0x16 (Deep Sleep)
idx 30 e0 e1 e2
val ff ff ff ff
def 20 20 04 05
LDN 0x17 (GPIOA)
idx e0 e1 e2 e3 e4 e5
val ff ff ff ff ff ff
def 01 00 00 00 01 00
4.
Output of flashrom -p internal -V on Ubuntu Server 18.04.5:
flashrom v0.9.9-r1954 on Linux 4.15.0-112-generic (x86_64)
flashrom is free software, get the source code at https://flashrom.org
flashrom was built with libpci 3.3.1, GCC 5.3.1 20160424, little endian
Command line (3 args): flashrom -p internal -V
Calibrating delay loop... OS timer resolution is 1 usecs, 3692M loops per
second, 10 myus = 9 us, 100 myus = 118 us, 1000 myus = 1031 us, 10000 myus =
9740 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Main Server Chassis"
DMI string system-manufacturer: "Supermicro"
DMI string system-product-name: "X10SL7-F"
DMI string system-version: "0123456789"
DMI string baseboard-manufacturer: "Supermicro"
DMI string baseboard-product-name: "X10SL7-F"
DMI string baseboard-version: "1.01 "
Found chipset "Intel C222" with PCI ID 8086:8c52.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to flash...@flashrom.org including a verbose (-V)
log.
Thank you!
Enabling flash write... Root Complex Register Block address = 0xfed1c000
GCS = 0xc61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI)
Top Swap: enabled (A16(+) inverted)
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode enabled
0xffe00000/0xffa00000 FWH decode enabled
0xffd80000/0xff980000 FWH decode enabled
0xffd00000/0xff900000 FWH decode enabled
0xffc80000/0xff880000 FWH decode enabled
0xffc00000/0xff800000 FWH decode enabled
0xff700000/0xff300000 FWH decode enabled
0xff600000/0xff200000 FWH decode enabled
0xff500000/0xff100000 FWH decode enabled
0xff400000/0xff000000 FWH decode enabled
Maximum FWH chip size: 0x100000 bytes
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x00007fb3b1769000 + 0x3800
0x04: 0xf008 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1
Warning: SPI Configuration Lockdown activated.
Reading OPCODES... done
0x06: 0x0000 (HSFC)
HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0
0x50: 0x00005a5b (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x5a, BRRA 0x5b
0x54: 0x000f0000 FREG0: Warning: Flash Descriptor region
(0x00000000-0x0000ffff) is read-only.
0x58: 0x0fff0500 FREG1: BIOS region (0x00500000-0x00ffffff) is read-write.
0x5C: 0x04ff0020 FREG2: Warning: Management Engine region
(0x00020000-0x004fffff) is locked.
0x60: 0x001f0010 FREG3: Gigabit Ethernet region (0x00010000-0x0001ffff) is
read-write.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME. Please see https://flashrom.org/ME for details.
Writes have been disabled for safety reasons. You can enforce write
support with the ich_spi_force programmer option, but you will most likely
harm your hardware! If you force flashrom you will get no support if
something breaks. On a few mainboards it is possible to enable write
access by setting a jumper (see its documentation or the board itself).
0x90: 0x80 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0x91: 0xf94010 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1
0x94: 0x0006 (PREOP)
0x96: 0x003b (OPTYPE)
0x98: 0x05200302 (OPMENU)
0x9C: 0x00009f9f (OPMENU+4)
0xA0: 0x00000000 (BBAR)
0xC4: 0x80802005 (LVSCC)
LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xC8: 0x00002005 (UVSCC)
UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
0xD0: 0x50444653 (FPB)
OK.
The following protocols are supported: FWH, SPI.
Found Micron/Numonyx/ST flash chip "N25Q128..3E" (16384 kB, SPI) mapped at
physical address 0x00000000ff000000.
Chip status register is 0x00.
Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set
Chip status register: Block Protect 3 (BP3) is not set
Chip status register: Top/Bottom (TB) is top
Chip status register: Block Protect 2 (BP2) is not set
Chip status register: Block Protect 1 (BP1) is not set
Chip status register: Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Found Micron/Numonyx/ST flash chip "N25Q128..3E" (16384 kB, SPI).
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
No operations were specified.
Restoring MMIO space at 0x7fb3b176c8a0
Restoring PCI config space for 00:1f:0 reg 0xdc
Segmentation fault (core dumped)
5.
https://www.supermicro.com/en/products/motherboard/X10SL7-F
_______________________________________________
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org
