=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2020.12.12 17:05:25 =~=~=~=~=~=~=~=~=~=~=~= System BootOrder not found. Initializing defaults. Creating boot entry "Boot0002" with label "ubuntu" for file "\EFI\ubuntu\shimx64.efi"  coreboot-4.0 Sat Dec 12 16:52:44 GMT 2020 starting... BIOS Version. KeWin_micro_2_01.07A RTC Init Starting the Intel FSP (early_init) PM1_STS = 0x2000 PM1_CNT = 0x0 GEN_PMCON1 = 0x1301a08 prev_sleep_state = S0 Configure Default UPD Data SPD Addr1: 0xa0 SPD Addr2: 0xa2 LPSS device mode: ACPI Tseg Size: 1 MB MMIO Size: 2048 MB IGD Memory Size: 64 MB Aperture Size: 256 MB GTT Size: 2 MB MIPI/ISP: Enabled Sdcard: Enabled Sata: Enabled SATA Mode: AHCI Lpe: Disabled Lpe mode: PCI SIO Dma 0: Enabled SIO I2C0: Enabled SIO I2C1: Enabled SIO I2C2: Enabled SIO I2C3: Enabled SIO I2C4: Enabled SIO I2C5: Enabled SIO I2C6: Enabled Azalia: Enabled SIO Dma1: Enabled Pwm0 Disabled Pwm1: Disabled Hsuart0: Enabled Hsuart1: Enabled Spi: Enabled Xhci: Enabled find_current_mrc_cache_local: picked entry 0 from cache block FSP MRC cache present at fff40000. ============= PEIM FSP v1.0 (VLYVIEW0 v0.0.3.5) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FF5 The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000 Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926 PcdMrcInitTsegSize = 1 PcdMrcInitMmioSize = 800 PcdMrcInitSPDAddr1 = A0 PcdMrcInitSPDAddr2 = A2 Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type AutoSelfRefreshEnable = 0x2 RID = 0x11. Reg_EFF_DualCH_EN = 0x40030180. CurrentMrcData.BootMode = 4 Taking Fastboot path! Configuring Memory Start... Configuring Memory End UpperTotalMemory = 0x80000000 dBMBOUND = 0x80000000 dBMBOUNDHI = 0x80000000 dGFXBase = 0x7BE00000 dTSegBase = 0x7BD00000 Save MRC params. Current MRC Data DDR Freq 1 Current MRC Data Core Freq 1 Current MRC Data Tcl 7 Current MRC Data WL 6 Current MRC Data DDRType 1 Current MRC Data MMIO Size 800 Current MRC Data TSeg Size 1 Channel 0 Enabled 1 Socket 0 DimmPresent 1 DimmDataWidth 1 DimmBusWidth 3 DimmSize 2 DimmSides 0 Channel 1 Enabled 0 Socket 0 DimmPresent 0 DimmDataWidth 0 DimmBusWidth 0 DimmSize 0 DimmSides 0 Current MRC Timing Data MRC_DATA_TRP 7 Current MRC Timing Data MRC_DATA_TRCD 7 Current MRC Timing Data MRC_DATA_TRAS 14 Current MRC Timing Data MRC_DATA_TWR 8 Current MRC Timing Data MRC_DATA_TWTR 4 Current MRC Timing Data MRC_DATA_TRRD 4 Current MRC Timing Data MRC_DATA_TRTP 4 Current MRC Timing Data MRC_DATA_TFAW 1B PeiInstallPeiMemory MemoryBegin 0x7B600000, MemoryLength 0x200000 Old Stack size 24576, New stack size 131072 Heap Offset = 0x0 Stack Offset = 0x838F0000 Stack Hob: BaseAddress=0x7B600000 Length=0x20000 Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFBFB38 Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F InstallVlvInitPpi() - Start Register PPI Notify: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 InstallVlvInitPpi() - End InstallPchInitPpi() - Start PmcBase needs to be programmed and enabled before here. ProgramGpioSCForSDCardWA Done.... Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D Register PPI Notify: 00B710BA-8CD6-4BF3-AB7A-9A24F54CC334 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7B7D23E9 PchModPhyProgramming() - Start SOC B0 and later ModPhy Table programming PchModPhyProgramming() - End PchSataInit() - Start PchSataInit() - End InstallPchInitPpi() - End Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 Register PPI Notify: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Number of BSP+AP: 1 Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C Install PPI: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3 Notify: PPI Guid: 7D84B2C2-22A1-4372-B12C-EBB232D3A6A3, Peim notify entry point: 7B7E329B VlvInitPeiEntryPoint start.... ------------------------ VLV SSA Platform Policy dump Begin --------------- Graphics Configuration: GttSize : 2 MB IgdDvmt50PreAlloc : 2 PrimaryDisplay : 0 ApertureSize : 2 Turbo Enable : 1 ------------------------ VLV SSA Platform Policy dump END ----------------- ProgramEcBase Done.... SSASafeConfiguration Done.... Clear Dbuff to all zero before read 0xFFFFFFFF PUNIT_ISPSSPM0 value is 0x3000003 ISP Device is enabled by fuse Skip ISPConfig InitThermalRegisters Done.... IGD enabled. IGD Turbo Enable. PUNIT_BIOS_CONFIG11 = 0x40030180. PUNIT_BIOS_CONFIG22 = 0x40030100. TotalMmioLength: 0x10400000 bytes GraphicsInit Done.... Install PPI: 09EA8911-BE0D-4230-A003-EDC693B48E11 Install mVlvPeiInitPpi Done.... Install PPI: 15344673-D365-4BE2-8513-1497CC07611D Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7B7D2A93 PchInitialize() - Start PchMiscInit() - Start [1] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 [2] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 [3] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 [4] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 [5] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 [6] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 [7] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 [8] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 [9] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 [10] Polling bit3 of R_PCH_PMC_MTPMC1 = 0008 PchPcieRpcInit() - Start PchPcieRpcInit() - End PchMiscInit() - End PchIoApicInit() - Start PchIoApicInit() - End PchPeimEhciPllCfg() SystemConfiguration->EhciPllCfgEnable = 0x0 PchInitialize() - End Install PPI: 5BAB88BA-E0E2-4674-B6AD-B812F6881CD6 Install PPI: F8BFF014-18FB-4EF9-B10C-AE22738DBEED B0 SCC eMMC 4.5 Configuration ConfigureSoCGpio------------start ConfigureSoCGpio------------end ConfigureLpssAndSccGpio------------start ConfigureLpssAndSccGpio------------end PchInitInterrupt () - Start PchInitInterrupt () - End ConfigureLpeGpio------------start ConfigureLpeGpio------------end Install PPI: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 Notify: PPI Guid: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5, Peim notify entry point: 7B7C7271 Initializing GT PowerManagement and other GT POST related Initializing GT PowerManagement Polling allow-wake bit PcBase = 0x7FEFA000 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Notify: PPI Guid: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5, Peim notify entry point: 7B7A6277 PchInitEntryPoint() Start PCH Base Addresses: ------------------- RCBA 0xFED1C000 PmcBase 0xFED03000 IoBase 0xFED0C000 IlbBase 0xFED08000 SpiBase 0xFED01000 MphyBase 0xFEF00000 AcpiBase 0x400 GpioBase 0x500 ------------------- InitializePchDevice() Start ConfigureMiscPm() Start ConfigureMiscPm() End ConfigureAdditionalPm() PchPlatformPolicy->EhciPllCfgEnable = 0x0 ConfigureMiscItems() Start ConfigureMiscItems() End ConfigureAzalia() Start Detected Azalia Codec with verb table, VendorID = 0x10EC0262 on SDI0, revision = 0x2. SDI1 has no Azalia device. Detected Azalia Codec with verb table, VendorID = 0x80862882 on SDI2, revision = 0x0. SDI3 has no Azalia device. ConfigureAzalia() End AzaliaEnable = 1 ConfigureOtg() Start USB3 OTG not present, skipping. ConfigureOtg() End ConfigureUsb() Start CommonUsbInit() - Start B2 or B2+ SOC on BayleyBay RVP USB2_PHY USB2_COMPBG:0x4700 USB2PHY reg(0x4100): 0x49A09 USB2PHY reg(0x4122): 0x300401D USB2PHY reg(0x4200): 0x49A09 USB2PHY reg(0x4222): 0x300401D USB2PHY reg(0x4300): 0x49209 USB2PHY reg(0x4322): 0x1004015 USB2PHY reg(0x4400): 0x49A09 USB2PHY reg(0x4422): 0x300401D CCU DIV_CTRL value ->0x3A08, cr_ush_clk_sel bit is 0x0 B2 or B2+ SOC on BayleyBay RVP USB2_PHY USB2_COMPBG:0x4700 USB2PHY reg(0x4100): 0x49A09 USB2PHY reg(0x4122): 0x300401D USB2PHY reg(0x4200): 0x49A09 USB2PHY reg(0x4222): 0x300401D USB2PHY reg(0x4300): 0x49209 USB2PHY reg(0x4322): 0x1004015 USB2PHY reg(0x4400): 0x49A09 USB2PHY reg(0x4422): 0x300401D set Late FID Check Disable:0x501037F UsbXhciLpmSupport enabled-->XhciM mioBase:0x-257949696 CDN_PHY R_PCH_CDN_PLL_CONTROL:0x73 CDN_PHY R_PCH_CDN_VCO_START_CALIBRATION_START_POINT:0xA Ccdrlf_configuration:0x1D46018B ree_peaking_amp_configuration_and_diagnostic :0x1FF ree_offset_correction_configuration_and_diagnostics:0x0 ree_vga_gain_configuration_and_diagnostics.:0x2F ree_dac_control.:0x249F0006 CDN_PHY R_PCH_CDN_U1_POWER_STATE_DEFINITION:0x1BCF Putting EHCI into D3 Hot State. CommonUsbInit() - End ConfigureUsb() End PchInitRootPorts() Start Root Port 1 device enabled. RpEnableMask: 0xF Root Port 2 device enabled. RpEnableMask: 0xF Root Port 3 device enabled. RpEnableMask: 0xF Root Port 4 device enabled. RpEnableMask: 0xF PchInitRootPorts() End ConfigureSata() Start ConfigureSata() End ConfigureLpe() Start Putting LPE Audio into D3 Hot State. ConfigureLpe() End ConfigureLpss() Start Putting LPSS1 PWM 0 into D3 Hot State. Putting LPSS1 PWM 1 into D3 Hot State. ConfigureLpss() End ConfigureScc() Start eMMC DLL Settings for BBAY. ConfigureDLLSettingForEMMC45: eMMC DLL Settings for BayleyBay . Putting SCC eMMC 4.41 into D3 Hot State. SCC SDIO not present, skipping. ConfigureSdCardCap: Overwride Capability Register ConfigureSdCardCap: New Capability Reg = 0x80000000-76864B2 SCC eMMC 4.5 not present, skipping. ConfigureScc() End ConfigureClockGating() Start ConfigureClockGating() End ConfigureIoApic() Start ConfigureIoApic() End ProgramSvidSid() Start Writing SVID/SID for B0/D31/F3 Writing SVID/SID for B0/D31/F0 Writing SVID/SID for B0/D30/F5 Writing SVID/SID for B0/D30/F4 Writing SVID/SID for B0/D30/F3 Writing SVID/SID for B0/D30/F0 Writing SVID/SID for B0/D28/F3 Writing SVID/SID for B0/D28/F2 Writing SVID/SID for B0/D28/F1 Writing SVID/SID for B0/D28/F0 Writing SVID/SID for B0/D27/F0 Writing SVID/SID for B0/D2/F0 Writing SVID/SID for B0/D24/F7 Writing SVID/SID for B0/D24/F6 Writing SVID/SID for B0/D24/F5 Writing SVID/SID for B0/D24/F4 Writing SVID/SID for B0/D24/F3 Writing SVID/SID for B0/D24/F2 Writing SVID/SID for B0/D24/F1 Writing SVID/SID for B0/D24/F0 Writing SVID/SID for B0/D20/F0 Writing SVID/SID for B0/D19/F0 Writing SVID/SID for B0/D18/F0 ProgramSvidSid() End InitializePchDevice() End Install PPI: D31F0400-7D16-4316-BF88-6065883B402B PchInitEntryPoint() End Register PPI Notify: CFB33810-6E87-4284-B203-A66ABE07F6E8 Detected Boot Mode 0 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B DXE IPL Entry FSP HOB is located at 0x7B620000 Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6 FSP is waiting for NOTIFY romstage_main_continue status: 0 hob_list_ptr: 7b620000 FSP Status: 0x0 PM1_STS = 0x2000 PM1_CNT = 0x0 GEN_PMCON1 = 0x1201808 romstage_main_continue: prev_sleep_state = S0 Baytrail Chip Variant: Bay Trail-I (ISG/embedded) MRC v0.102 1 channels of DDR3 @ 1066MHz CBMEM: root @ 7b5ff000 254 entries. Trying CBFS ramstage loader. CBFS: loading stage fallback/ramstage @ 0x100000 (290872 bytes), entry @ 0x100000 coreboot-4.0 Sat Dec 12 16:52:44 GMT 2020 booting... clocks_per_usec: 1466 CBMEM: recovering 3/254 entries from root @ 7b5ff000 Moving GDT to 7b5fc000...ok BS: BS_PRE_DEVICE times (us): entry 8068 run 0 exit 0 CPUID: 00030679 Cores: 1 Revision ID: 11 Stepping: D1 msr(17) = 0000000c90040b3a msr(ce) = 0000040000000b00 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 11313 exit 0 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:17.0: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 1 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 0 PCI: 00:1e.3: enabled 1 PCI: 00:1e.4: enabled 1 PCI: 00:1e.5: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.3: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:17.0: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 1 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 0 PCI: 00:1e.3: enabled 1 PCI: 00:1e.4: enabled 1 PCI: 00:1e.5: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.3: enabled 1 scan_static_bus for Root Device enable_dev(Intel BayTrail SoC, 7) CPU_CLUSTER: 0 enabled enable_dev(Intel BayTrail SoC, 6) DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 enable_dev(Intel BayTrail SoC, 2) PCI: 00:00.0 [8086/0f00] ops fsp_header_ptr: fffb0094 FSP Header Version: 1 FSP Revision: 3.5 PCI: 00:00.0 [8086/0f00] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:02.0 [8086/0f31] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:03.0: Disabling device: 03.0 Capability: type 0xff @ 0xfc Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:10.0: Disabling device: 10.0 Capability: type 0xff @ 0xfc Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:11.0: Device Disable - Override Soft Strap: 11.0 PCI: 00:11.0: Disabling device: 11.0 VL179 - Do not place: 11.0 in D3 enable_dev(Intel BayTrail SoC, 2) PCI: 00:12.0 [8086/0f16] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:13.0 [8086/0f23] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:14.0 [8086/0f35] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:15.0: Disabling device: 15.0 Capability: type 0xff @ 0xfc Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:16.0: Disabling device: 16.0 Capability: type 0xff @ 0xfc Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:17.0: Device Disable - Override Soft Strap: 17.0 PCI: 00:17.0: Disabling device: 17.0 Capability: type 0xff @ 0xfc Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.0 [8086/0f40] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.1 [8086/0f41] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.2 [8086/0f42] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.3 [8086/0f43] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.4 [8086/0f44] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.5 [8086/0f45] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.6 [8086/0f46] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.7 [8086/0f47] enabled enable_dev(Intel BayTrail SoC, 2) PCI: Static device PCI: 00:1a.0 not found, disabling it. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1b.0 [8086/0f04] enabled enable_dev(Intel BayTrail SoC, 2) Capability: type 0x10 @ 0x40 Capability: type 0x05 @ 0x80 Capability: type 0x0d @ 0x90 Capability: type 0x01 @ 0xa0 Capability: type 0x10 @ 0x40 PCI: 00:1c.0 subordinate bus PCI Express PCI: 00:1c.0 [8086/0f48] enabled enable_dev(Intel BayTrail SoC, 2) Capability: type 0x10 @ 0x40 Capability: type 0x05 @ 0x80 Capability: type 0x0d @ 0x90 Capability: type 0x01 @ 0xa0 Capability: type 0x10 @ 0x40 PCI: 00:1c.1 subordinate bus PCI Express PCI: 00:1c.1 [8086/0f4a] enabled enable_dev(Intel BayTrail SoC, 2) Capability: type 0x10 @ 0x40 Capability: type 0x05 @ 0x80 Capability: type 0x0d @ 0x90 Capability: type 0x01 @ 0xa0 Capability: type 0x10 @ 0x40 PCI: 00:1c.2 subordinate bus PCI Express PCI: 00:1c.2 [8086/0f4c] enabled enable_dev(Intel BayTrail SoC, 2) Capability: type 0x10 @ 0x40 Capability: type 0x05 @ 0x80 Capability: type 0x0d @ 0x90 Capability: type 0x01 @ 0xa0 Capability: type 0x10 @ 0x40 PCI: 00:1c.3 subordinate bus PCI Express PCI: 00:1c.3 [8086/0f4e] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1d.0: Disabling device: 1d.0 Capability: type 0xff @ 0xfc Power management CAP offset 0x70. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.0 [8086/0f06] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.1: Disabling device: 1e.1 Capability: type 0xff @ 0xfc Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.2: Disabling device: 1e.2 Capability: type 0xff @ 0xfc Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.3 [8086/0f0a] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.4 [8086/0f0c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.5 [8086/0f0e] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1f.0 [8086/0f1c] bus ops PCI: 00:1f.0 [8086/0f1c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1f.3 [8086/0f12] enabled do_pci_scan_bridge for PCI: 00:1c.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:1c.1 PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [168c/003e] enabled PCI: pci_scan_bus returning with max=002 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x10 @ 0x40 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:1c.2 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/1539] enabled PCI: pci_scan_bus returning with max=003 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x11 @ 0x70 Capability: type 0x10 @ 0xa0 Capability: type 0x10 @ 0x40 Enabling Common Clock Configuration ASPM: Enabled L1 do_pci_scan_bridge returns max 3 do_pci_scan_bridge for PCI: 00:1c.3 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 scan_static_bus for PCI: 00:1f.0 scan_static_bus for PCI: 00:1f.0 done PCI: pci_scan_bus returning with max=004 scan_static_bus for Root Device done done BS: BS_DEV_ENUMERATE times (us): entry 0 run 722172 exit 0 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 UMA, GTT & SMM memory location: 0x7bd00000 UMA, GTT & SMM memory size: 67M FSP memory location: 0x7b600000 FSP memory size: 7M Warning: Fsp memory size does not match expected memory size (200000). Available memory below 4GB: 0x7b600000 (1974M) Available memory above 4GB: 0M Adding PCIe config bar base=0xe0000000 size=0x10000000 PCI: 00:1c.0 read_resources bus 1 link: 0 PCI: 00:1c.0 read_resources bus 1 link: 0 done PCI: 00:1c.1 read_resources bus 2 link: 0 PCI: 00:1c.1 read_resources bus 2 link: 0 done PCI: 00:1c.2 read_resources bus 3 link: 0 PCI: 00:1c.2 read_resources bus 3 link: 0 done PCI: 00:1c.3 read_resources bus 4 link: 0 PCI: 00:1c.3 read_resources bus 4 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7b500000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7b600000 size 4a00000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffff flags 200 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20 PCI: 00:03.0 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:13.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:13.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:13.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:13.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:13.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24 PCI: 00:14.0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.0 PCI: 00:16.0 PCI: 00:17.0 PCI: 00:18.0 PCI: 00:18.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:18.1 PCI: 00:18.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:18.2 PCI: 00:18.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:18.4 PCI: 00:18.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:18.5 PCI: 00:18.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:18.6 PCI: 00:18.6 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.6 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:18.7 PCI: 00:18.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:1a.0 PCI: 00:1b.0 PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:1c.0 PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:1c.1 child on link 0 PCI: 02:00.0 PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:1c.2 child on link 0 PCI: 03:00.0 PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:1c.3 PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1e.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:1e.1 PCI: 00:1e.2 PCI: 00:1e.3 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:1e.4 PCI: 00:1e.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:1e.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:1e.5 PCI: 00:1e.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:1e.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:1f.0 PCI: 00:1f.0 resource base feb00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index feb PCI: 00:1f.0 resource base fed03000 size 400 align 0 gran 0 limit 0 flags f0000200 index 44 PCI: 00:1f.0 resource base fed0c000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4c PCI: 00:1f.0 resource base fed08000 size 400 align 0 gran 0 limit 0 flags f0000200 index 50 PCI: 00:1f.0 resource base fed01000 size 400 align 0 gran 0 limit 0 flags f0000200 index 54 PCI: 00:1f.0 resource base fef00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 58 PCI: 00:1f.0 resource base fed05000 size 800 align 0 gran 0 limit 0 flags f0000200 index 5c PCI: 00:1f.0 resource base fed1c000 size 400 align 0 gran 0 limit 0 flags f0000200 index f0 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index fff PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index fec PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffffffff flags 200 index 10 PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 03:00.0 18 * [0x0 - 0x1f] io PCI: 00:1c.2 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1c.2 1c * [0x0 - 0xfff] io PCI: 00:13.0 20 * [0x1000 - 0x101f] io PCI: 00:1f.3 20 * [0x1020 - 0x103f] io PCI: 00:02.0 20 * [0x1040 - 0x1047] io PCI: 00:13.0 10 * [0x1048 - 0x104f] io PCI: 00:13.0 18 * [0x1050 - 0x1057] io PCI: 00:13.0 14 * [0x1058 - 0x105b] io PCI: 00:13.0 1c * [0x105c - 0x105f] io DOMAIN: 0000 compute_resources_io: base: 1060 size: 1060 align: 12 gran: 0 limit: ffff done DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:1c.1 compute_resources_mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem PCI: 00:1c.2 compute_resources_mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem PCI: 00:1c.1 20 * [0x10400000 - 0x105fffff] mem PCI: 00:1c.2 20 * [0x10600000 - 0x106fffff] mem PCI: 00:14.0 10 * [0x10700000 - 0x1070ffff] mem PCI: 00:18.0 10 * [0x10710000 - 0x10713fff] mem PCI: 00:1b.0 10 * [0x10714000 - 0x10717fff] mem PCI: 00:1e.0 10 * [0x10718000 - 0x1071bfff] mem PCI: 00:12.0 10 * [0x1071c000 - 0x1071cfff] mem PCI: 00:12.0 14 * [0x1071d000 - 0x1071dfff] mem PCI: 00:18.0 14 * [0x1071e000 - 0x1071efff] mem PCI: 00:18.1 10 * [0x1071f000 - 0x1071ffff] mem PCI: 00:18.1 14 * [0x10720000 - 0x10720fff] mem PCI: 00:18.2 10 * [0x10721000 - 0x10721fff] mem PCI: 00:18.2 14 * [0x10722000 - 0x10722fff] mem PCI: 00:18.3 10 * [0x10723000 - 0x10723fff] mem PCI: 00:18.3 14 * [0x10724000 - 0x10724fff] mem PCI: 00:18.4 10 * [0x10725000 - 0x10725fff] mem PCI: 00:18.4 14 * [0x10726000 - 0x10726fff] mem PCI: 00:18.5 10 * [0x10727000 - 0x10727fff] mem PCI: 00:18.5 14 * [0x10728000 - 0x10728fff] mem PCI: 00:18.6 10 * [0x10729000 - 0x10729fff] mem PCI: 00:18.6 14 * [0x1072a000 - 0x1072afff] mem PCI: 00:18.7 10 * [0x1072b000 - 0x1072bfff] mem PCI: 00:18.7 14 * [0x1072c000 - 0x1072cfff] mem PCI: 00:1e.0 14 * [0x1072d000 - 0x1072dfff] mem PCI: 00:1e.3 10 * [0x1072e000 - 0x1072efff] mem PCI: 00:1e.3 14 * [0x1072f000 - 0x1072ffff] mem PCI: 00:1e.4 10 * [0x10730000 - 0x10730fff] mem PCI: 00:1e.4 14 * [0x10731000 - 0x10731fff] mem PCI: 00:1e.5 10 * [0x10732000 - 0x10732fff] mem PCI: 00:1e.5 14 * [0x10733000 - 0x10733fff] mem PCI: 00:13.0 24 * [0x10734000 - 0x107347ff] mem PCI: 00:1f.3 10 * [0x10734800 - 0x1073481f] mem DOMAIN: 0000 compute_resources_mem: base: 10734820 size: 10734820 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:14.0 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 constrain_resources: PCI: 00:18.5 constrain_resources: PCI: 00:18.6 constrain_resources: PCI: 00:18.7 constrain_resources: PCI: 00:1b.0 constrain_resources: PCI: 00:1c.0 constrain_resources: PCI: 00:1c.1 constrain_resources: PCI: 02:00.0 constrain_resources: PCI: 00:1c.2 constrain_resources: PCI: 03:00.0 constrain_resources: PCI: 00:1c.3 constrain_resources: PCI: 00:1e.0 constrain_resources: PCI: 00:1e.3 constrain_resources: PCI: 00:1e.4 constrain_resources: PCI: 00:1e.5 constrain_resources: PCI: 00:1f.0 constrain_resources: PCI: 00:1f.3 avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff lim->base 80000000 lim->limit dfffffff Setting resources... DOMAIN: 0000 allocate_resources_io: base:1000 size:1060 align:12 gran:0 limit:ffff Assigned: PCI: 00:1c.2 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:13.0 20 * [0x2000 - 0x201f] io Assigned: PCI: 00:1f.3 20 * [0x2020 - 0x203f] io Assigned: PCI: 00:02.0 20 * [0x2040 - 0x2047] io Assigned: PCI: 00:13.0 10 * [0x2048 - 0x204f] io Assigned: PCI: 00:13.0 18 * [0x2050 - 0x2057] io Assigned: PCI: 00:13.0 14 * [0x2058 - 0x205b] io Assigned: PCI: 00:13.0 1c * [0x205c - 0x205f] io DOMAIN: 0000 allocate_resources_io: next_base: 2060 size: 1060 align: 12 gran: 0 done PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:1c.2 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 03:00.0 18 * [0x1000 - 0x101f] io PCI: 00:1c.2 allocate_resources_io: next_base: 1020 size: 1000 align: 12 gran: 12 done PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:10734820 align:28 gran:0 limit:dfffffff Assigned: PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem Assigned: PCI: 00:02.0 10 * [0xd0000000 - 0xd03fffff] mem Assigned: PCI: 00:1c.1 20 * [0xd0400000 - 0xd05fffff] mem Assigned: PCI: 00:1c.2 20 * [0xd0600000 - 0xd06fffff] mem Assigned: PCI: 00:14.0 10 * [0xd0700000 - 0xd070ffff] mem Assigned: PCI: 00:18.0 10 * [0xd0710000 - 0xd0713fff] mem Assigned: PCI: 00:1b.0 10 * [0xd0714000 - 0xd0717fff] mem Assigned: PCI: 00:1e.0 10 * [0xd0718000 - 0xd071bfff] mem Assigned: PCI: 00:12.0 10 * [0xd071c000 - 0xd071cfff] mem Assigned: PCI: 00:12.0 14 * [0xd071d000 - 0xd071dfff] mem Assigned: PCI: 00:18.0 14 * [0xd071e000 - 0xd071efff] mem Assigned: PCI: 00:18.1 10 * [0xd071f000 - 0xd071ffff] mem Assigned: PCI: 00:18.1 14 * [0xd0720000 - 0xd0720fff] mem Assigned: PCI: 00:18.2 10 * [0xd0721000 - 0xd0721fff] mem Assigned: PCI: 00:18.2 14 * [0xd0722000 - 0xd0722fff] mem Assigned: PCI: 00:18.3 10 * [0xd0723000 - 0xd0723fff] mem Assigned: PCI: 00:18.3 14 * [0xd0724000 - 0xd0724fff] mem Assigned: PCI: 00:18.4 10 * [0xd0725000 - 0xd0725fff] mem Assigned: PCI: 00:18.4 14 * [0xd0726000 - 0xd0726fff] mem Assigned: PCI: 00:18.5 10 * [0xd0727000 - 0xd0727fff] mem Assigned: PCI: 00:18.5 14 * [0xd0728000 - 0xd0728fff] mem Assigned: PCI: 00:18.6 10 * [0xd0729000 - 0xd0729fff] mem Assigned: PCI: 00:18.6 14 * [0xd072a000 - 0xd072afff] mem Assigned: PCI: 00:18.7 10 * [0xd072b000 - 0xd072bfff] mem Assigned: PCI: 00:18.7 14 * [0xd072c000 - 0xd072cfff] mem Assigned: PCI: 00:1e.0 14 * [0xd072d000 - 0xd072dfff] mem Assigned: PCI: 00:1e.3 10 * [0xd072e000 - 0xd072efff] mem Assigned: PCI: 00:1e.3 14 * [0xd072f000 - 0xd072ffff] mem Assigned: PCI: 00:1e.4 10 * [0xd0730000 - 0xd0730fff] mem Assigned: PCI: 00:1e.4 14 * [0xd0731000 - 0xd0731fff] mem Assigned: PCI: 00:1e.5 10 * [0xd0732000 - 0xd0732fff] mem Assigned: PCI: 00:1e.5 14 * [0xd0733000 - 0xd0733fff] mem Assigned: PCI: 00:13.0 24 * [0xd0734000 - 0xd07347ff] mem Assigned: PCI: 00:1f.3 10 * [0xd0734800 - 0xd073481f] mem DOMAIN: 0000 allocate_resources_mem: next_base: d0734820 size: 10734820 align: 28 gran: 0 done PCI: 00:1c.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:1c.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:1c.1 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.1 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:1c.1 allocate_resources_mem: base:d0400000 size:200000 align:21 gran:20 limit:dfffffff Assigned: PCI: 02:00.0 10 * [0xd0400000 - 0xd05fffff] mem PCI: 00:1c.1 allocate_resources_mem: next_base: d0600000 size: 200000 align: 21 gran: 20 done PCI: 00:1c.2 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.2 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:1c.2 allocate_resources_mem: base:d0600000 size:100000 align:20 gran:20 limit:dfffffff Assigned: PCI: 03:00.0 10 * [0xd0600000 - 0xd061ffff] mem Assigned: PCI: 03:00.0 1c * [0xd0620000 - 0xd0623fff] mem PCI: 00:1c.2 allocate_resources_mem: next_base: d0624000 size: 100000 align: 20 gran: 20 done PCI: 00:1c.3 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.3 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:1c.3 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:1c.3 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d03fffff] size 0x00400000 gran 0x16 mem PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:02.0 20 <- [0x0000002040 - 0x0000002047] size 0x00000008 gran 0x03 io PCI: 00:12.0 10 <- [0x00d071c000 - 0x00d071cfff] size 0x00001000 gran 0x0c mem PCI: 00:12.0 14 <- [0x00d071d000 - 0x00d071dfff] size 0x00001000 gran 0x0c mem PCI: 00:13.0 10 <- [0x0000002048 - 0x000000204f] size 0x00000008 gran 0x03 io PCI: 00:13.0 14 <- [0x0000002058 - 0x000000205b] size 0x00000004 gran 0x02 io PCI: 00:13.0 18 <- [0x0000002050 - 0x0000002057] size 0x00000008 gran 0x03 io PCI: 00:13.0 1c <- [0x000000205c - 0x000000205f] size 0x00000004 gran 0x02 io PCI: 00:13.0 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 00:13.0 24 <- [0x00d0734000 - 0x00d07347ff] size 0x00000800 gran 0x0b mem PCI: 00:14.0 10 <- [0x00d0700000 - 0x00d070ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:18.0 10 <- [0x00d0710000 - 0x00d0713fff] size 0x00004000 gran 0x0e mem PCI: 00:18.0 14 <- [0x00d071e000 - 0x00d071efff] size 0x00001000 gran 0x0c mem PCI: 00:18.1 10 <- [0x00d071f000 - 0x00d071ffff] size 0x00001000 gran 0x0c mem PCI: 00:18.1 14 <- [0x00d0720000 - 0x00d0720fff] size 0x00001000 gran 0x0c mem PCI: 00:18.2 10 <- [0x00d0721000 - 0x00d0721fff] size 0x00001000 gran 0x0c mem PCI: 00:18.2 14 <- [0x00d0722000 - 0x00d0722fff] size 0x00001000 gran 0x0c mem PCI: 00:18.3 10 <- [0x00d0723000 - 0x00d0723fff] size 0x00001000 gran 0x0c mem PCI: 00:18.3 14 <- [0x00d0724000 - 0x00d0724fff] size 0x00001000 gran 0x0c mem PCI: 00:18.4 10 <- [0x00d0725000 - 0x00d0725fff] size 0x00001000 gran 0x0c mem PCI: 00:18.4 14 <- [0x00d0726000 - 0x00d0726fff] size 0x00001000 gran 0x0c mem PCI: 00:18.5 10 <- [0x00d0727000 - 0x00d0727fff] size 0x00001000 gran 0x0c mem PCI: 00:18.5 14 <- [0x00d0728000 - 0x00d0728fff] size 0x00001000 gran 0x0c mem PCI: 00:18.6 10 <- [0x00d0729000 - 0x00d0729fff] size 0x00001000 gran 0x0c mem PCI: 00:18.6 14 <- [0x00d072a000 - 0x00d072afff] size 0x00001000 gran 0x0c mem PCI: 00:18.7 10 <- [0x00d072b000 - 0x00d072bfff] size 0x00001000 gran 0x0c mem PCI: 00:18.7 14 <- [0x00d072c000 - 0x00d072cfff] size 0x00001000 gran 0x0c mem PCI: 00:1b.0 10 <- [0x00d0714000 - 0x00d0717fff] size 0x00004000 gran 0x0e mem64 PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:1c.1 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:1c.1 20 <- [0x00d0400000 - 0x00d05fffff] size 0x00200000 gran 0x14 bus 02 mem PCI: 00:1c.1 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00d0400000 - 0x00d05fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:1c.1 assign_resources, bus 2 link: 0 PCI: 00:1c.2 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:1c.2 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:1c.2 20 <- [0x00d0600000 - 0x00d06fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:1c.2 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x00d0600000 - 0x00d061ffff] size 0x00020000 gran 0x11 mem PCI: 03:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io PCI: 03:00.0 1c <- [0x00d0620000 - 0x00d0623fff] size 0x00004000 gran 0x0e mem PCI: 00:1c.2 assign_resources, bus 3 link: 0 PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:1c.3 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:1c.3 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 mem PCI: 00:1e.0 10 <- [0x00d0718000 - 0x00d071bfff] size 0x00004000 gran 0x0e mem PCI: 00:1e.0 14 <- [0x00d072d000 - 0x00d072dfff] size 0x00001000 gran 0x0c mem PCI: 00:1e.3 10 <- [0x00d072e000 - 0x00d072efff] size 0x00001000 gran 0x0c mem PCI: 00:1e.3 14 <- [0x00d072f000 - 0x00d072ffff] size 0x00001000 gran 0x0c mem PCI: 00:1e.4 10 <- [0x00d0730000 - 0x00d0730fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.4 14 <- [0x00d0731000 - 0x00d0731fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.5 10 <- [0x00d0732000 - 0x00d0732fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.5 14 <- [0x00d0733000 - 0x00d0733fff] size 0x00001000 gran 0x0c mem PCI: 00:1f.3 10 <- [0x00d0734800 - 0x00d073481f] size 0x00000020 gran 0x05 mem PCI: 00:1f.3 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 1060 align 12 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base c0000000 size 10734820 align 28 gran 0 limit dfffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7b500000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7b600000 size 4a00000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:02.0 PCI: 00:02.0 resource base d0000000 size 400000 align 22 gran 22 limit dfffffff flags 60000200 index 10 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001200 index 18 PCI: 00:02.0 resource base 2040 size 8 align 3 gran 3 limit ffff flags 60000100 index 20 PCI: 00:03.0 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.0 resource base d071c000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:12.0 resource base d071d000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:13.0 PCI: 00:13.0 resource base 2048 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:13.0 resource base 2058 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:13.0 resource base 2050 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:13.0 resource base 205c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:13.0 resource base 2000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:13.0 resource base d0734000 size 800 align 11 gran 11 limit dfffffff flags 60000200 index 24 PCI: 00:14.0 PCI: 00:14.0 resource base d0700000 size 10000 align 16 gran 16 limit dfffffff flags 60000201 index 10 PCI: 00:15.0 PCI: 00:16.0 PCI: 00:17.0 PCI: 00:18.0 PCI: 00:18.0 resource base d0710000 size 4000 align 14 gran 14 limit dfffffff flags 60000200 index 10 PCI: 00:18.0 resource base d071e000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:18.1 PCI: 00:18.1 resource base d071f000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:18.1 resource base d0720000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:18.2 PCI: 00:18.2 resource base d0721000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:18.2 resource base d0722000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:18.3 PCI: 00:18.3 resource base d0723000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:18.3 resource base d0724000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:18.4 PCI: 00:18.4 resource base d0725000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:18.4 resource base d0726000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:18.5 PCI: 00:18.5 resource base d0727000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:18.5 resource base d0728000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:18.6 PCI: 00:18.6 resource base d0729000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:18.6 resource base d072a000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:18.7 PCI: 00:18.7 resource base d072b000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:18.7 resource base d072c000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:1a.0 PCI: 00:1b.0 PCI: 00:1b.0 resource base d0714000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10 PCI: 00:1c.0 PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:1c.1 child on link 0 PCI: 02:00.0 PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.1 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:1c.1 resource base d0400000 size 200000 align 21 gran 20 limit dfffffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base d0400000 size 200000 align 21 gran 21 limit dfffffff flags 60000201 index 10 PCI: 00:1c.2 child on link 0 PCI: 03:00.0 PCI: 00:1c.2 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.2 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:1c.2 resource base d0600000 size 100000 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base d0600000 size 20000 align 17 gran 17 limit dfffffff flags 60000200 index 10 PCI: 03:00.0 resource base 1000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 PCI: 03:00.0 resource base d0620000 size 4000 align 14 gran 14 limit dfffffff flags 60000200 index 1c PCI: 00:1c.3 PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.3 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:1c.3 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:1d.0 PCI: 00:1e.0 PCI: 00:1e.0 resource base d0718000 size 4000 align 14 gran 14 limit dfffffff flags 60000200 index 10 PCI: 00:1e.0 resource base d072d000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:1e.1 PCI: 00:1e.2 PCI: 00:1e.3 PCI: 00:1e.3 resource base d072e000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:1e.3 resource base d072f000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:1e.4 PCI: 00:1e.4 resource base d0730000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:1e.4 resource base d0731000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:1e.5 PCI: 00:1e.5 resource base d0732000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:1e.5 resource base d0733000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 14 PCI: 00:1f.0 PCI: 00:1f.0 resource base feb00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index feb PCI: 00:1f.0 resource base fed03000 size 400 align 0 gran 0 limit 0 flags f0000200 index 44 PCI: 00:1f.0 resource base fed0c000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4c PCI: 00:1f.0 resource base fed08000 size 400 align 0 gran 0 limit 0 flags f0000200 index 50 PCI: 00:1f.0 resource base fed01000 size 400 align 0 gran 0 limit 0 flags f0000200 index 54 PCI: 00:1f.0 resource base fef00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 58 PCI: 00:1f.0 resource base fed05000 size 800 align 0 gran 0 limit 0 flags f0000200 index 5c PCI: 00:1f.0 resource base fed1c000 size 400 align 0 gran 0 limit 0 flags f0000200 index f0 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index fff PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index fec PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.3 PCI: 00:1f.3 resource base d0734800 size 20 align 5 gran 5 limit dfffffff flags 60000200 index 10 PCI: 00:1f.3 resource base 2020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 3286769 exit 0 Enabling resources... PCI: 00:02.0 subsystem <- 0000/0000 PCI: 00:02.0 cmd <- 07 PCI: 00:12.0 subsystem <- 0000/0000 PCI: 00:12.0 cmd <- 106 PCI: 00:13.0 subsystem <- 0000/0000 PCI: 00:13.0 cmd <- 107 PCI: 00:14.0 subsystem <- 0000/0000 PCI: 00:14.0 cmd <- 102 PCI: 00:18.0 subsystem <- 0000/0000 PCI: 00:18.0 cmd <- 106 PCI: 00:18.1 subsystem <- 0000/0000 PCI: 00:18.1 cmd <- 102 PCI: 00:18.2 subsystem <- 0000/0000 PCI: 00:18.2 cmd <- 102 PCI: 00:18.3 subsystem <- 0000/0000 PCI: 00:18.3 cmd <- 102 PCI: 00:18.4 subsystem <- 0000/0000 PCI: 00:18.4 cmd <- 102 PCI: 00:18.5 subsystem <- 0000/0000 PCI: 00:18.5 cmd <- 102 PCI: 00:18.6 subsystem <- 0000/0000 PCI: 00:18.6 cmd <- 102 PCI: 00:18.7 subsystem <- 0000/0000 PCI: 00:18.7 cmd <- 102 PCI: 00:1b.0 subsystem <- 0000/0000 PCI: 00:1b.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 cmd <- 100 PCI: 00:1c.1 bridge ctrl <- 0003 PCI: 00:1c.1 cmd <- 106 PCI: 00:1c.2 bridge ctrl <- 0003 PCI: 00:1c.2 cmd <- 107 PCI: 00:1c.3 bridge ctrl <- 0003 PCI: 00:1c.3 cmd <- 100 PCI: 00:1e.0 subsystem <- 0000/0000 PCI: 00:1e.0 cmd <- 106 PCI: 00:1e.3 subsystem <- 0000/0000 PCI: 00:1e.3 cmd <- 102 PCI: 00:1e.4 subsystem <- 0000/0000 PCI: 00:1e.4 cmd <- 102 PCI: 00:1e.5 subsystem <- 0000/0000 PCI: 00:1e.5 cmd <- 102 PCI: 00:1f.3 subsystem <- 0000/0000 PCI: 00:1f.3 cmd <- 103 PCI: 02:00.0 cmd <- 02 PCI: 03:00.0 cmd <- 03 done. BS: BS_DEV_ENABLE times (us): entry 0 run 139010 exit 0 Initializing devices... Root Device init Root Device init 1750 usecs CPU_CLUSTER: 0 init MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x00 done. CPU: Intel(R) Atom(TM) CPU E3815 @ 1.46GHz. Loading module at 00030000 with entry 00030000. filesize: 0x140 memsize: 0x140 Processing 16 relocs. Offset value of 0x00030000 Initializing CPU #0 CPU: vendor Intel device 30679 CPU: family 06, model 37, stepping 09 Init BayTrail core. CPU #0 initialized CPU_CLUSTER: 0 init 43174 usecs PCI: 00:02.0 init In CBFS, ROM address for PCI: 00:02.0 = ffe004f8 PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 PCI ROM image, vendor ID 8086, device ID 0f31, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from ffe004f8 to 0xc0000, 0x10000 bytes Real mode stub @00000600: 1123 bytes Calling Option ROM... ... Option ROM returned. Retrieving Edid Data via INT10h Parsing EDID Data Check EDID Established Timing Check EDID Standard Timing Check EDID DTD for additional modes EDID DTD Timing HRes: 1024 ,VRes: 768, DTD ValidEdidTiming->Key[0]: 0xb00 EDID: Header[0]: 0x0 Header[1]: 0xff Header[2]: 0xff Header[3]: 0xff Header[4]: 0xff Header[5]: 0xff Header[6]: 0xff Header[7]: 0x0 u16 ManufactureName: 0xa22c u16 ProductCode: 0x2851 u32 SerialNumber: 0x0 u8 WeekOfManufacture: 30 u8 YearOfManufacture: 28 u8 EdidVersion: 1 u8 EdidRevision: 4 u8 VideoInputDefinition: 0xa5 u8 MaxHorizontalImageSize: 0 u8 MaxVerticalImageSize: 0 u8 DisplayTransferCharacteristic: 0x0 u8 FeatureSupport: 0x2 u8 RedGreenLowBits: 0x0 u8 BlueWhiteLowBits: 0x0 u8 RedX: 0x0 u8 RedY: 0x0 u8 GreenX: 0x0 u8 GreenY: 0x0 u8 BlueX: 0x0 u8 BlueY: 0x0 u8 WhiteX: 0x0 u8 WhiteY: 0x0 EstablishedTimings[0]: 0x0 EstablishedTimings[1]: 0x0 EstablishedTimings[2]: 0x0 Standard Timing Bytes Byte[38]: 0x1 Byte[39]: 0x0 Byte[40]: 0x1 Byte[41]: 0x0 Byte[42]: 0x1 Byte[43]: 0x0 Byte[44]: 0x1 Byte[45]: 0x0 Byte[46]: 0x1 Byte[47]: 0x0 Byte[48]: 0x1 Byte[49]: 0x0 Byte[50]: 0x1 Byte[51]: 0x0 Byte[52]: 0x1 Byte[53]: 0x0 Descriptor Block Bytes Byte[54]: 0x64 Byte[55]: 0x19 Byte[56]: 0x0 Byte[57]: 0x40 Byte[58]: 0x41 Byte[59]: 0x0 Byte[60]: 0x26 Byte[61]: 0x30 Byte[62]: 0x1e Byte[63]: 0x64 Byte[64]: 0xae Byte[65]: 0x1 Byte[66]: 0x0 Byte[67]: 0x0 Byte[68]: 0x0 Byte[69]: 0x0 Byte[70]: 0x0 Byte[71]: 0x18 Byte[72]: 0x0 Byte[73]: 0x0 Byte[74]: 0x0 Byte[75]: 0xfc Byte[76]: 0x0 Byte[77]: 0x4b Byte[78]: 0x45 Byte[79]: 0x57 Byte[80]: 0x49 Byte[81]: 0x4e Byte[82]: 0x5f Byte[83]: 0x31 Byte[84]: 0x35 Byte[85]: 0x5f Byte[86]: 0x58 Byte[87]: 0x47 Byte[88]: 0x41 Byte[89]: 0xa Byte[90]: 0x0 Byte[91]: 0x0 Byte[92]: 0x0 Byte[93]: 0x10 Byte[94]: 0x0 Byte[95]: 0x0 Byte[96]: 0x0 Byte[97]: 0x0 Byte[98]: 0x0 Byte[99]: 0x0 Byte[100]: 0x0 Byte[101]: 0x0 Byte[102]: 0x0 Byte[103]: 0x0 Byte[104]: 0x0 Byte[105]: 0x0 Byte[106]: 0x0 Byte[107]: 0x0 Byte[108]: 0x0 Byte[109]: 0x0 Byte[110]: 0x0 Byte[111]: 0x10 Byte[112]: 0x0 Byte[113]: 0x0 Byte[114]: 0x0 Byte[115]: 0x0 Byte[116]: 0x0 Byte[117]: 0x0 Byte[118]: 0x0 Byte[119]: 0x0 Byte[120]: 0x0 Byte[121]: 0x0 Byte[122]: 0x0 Byte[123]: 0x0 Byte[124]: 0x0 Byte[125]: 0x0 u8 ExtensionFlag: 0x0 u8 Checksum: 0x8c Valid EDID retrieved: --------------------- Check driver-controller support for each available mode Retrieving available VESA modes via INT10h VESA_INFO u32 VesaSignature: 41534556 u16 VesaVersion: 300 u32 OemStringPtr: 724 u32 Capabilities: 1 u32 VideoModePtr: 664 u16 TotalMemory: 3df u16 OemSoftwareRev: 100 u16 OemVendorNamePtr: 770 u32 OemProductNamePtr: 782 u32 OemProductRevPtr: 797 Walk through available mode list at 0x00132330 looking for best EDID match Checking Mode Number: 0x160 Mode not supported Checking Mode Number: 0x161 Mode not supported Checking Mode Number: 0x162 Mode not supported Checking Mode Number: 0x163 Mode not supported Checking Mode Number: 0x164 Mode not supported Checking Mode Number: 0x165 Mode not supported Checking Mode Number: 0x166 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 1024 u16 x_resolution: 1024 u16 y_resolution: 600 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 8 u32 phys_base_ptr: 0xc0000000 Bits_per_pixel not 32 bit colour Checking Mode Number: 0x167 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 2048 u16 x_resolution: 1024 u16 y_resolution: 600 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 16 u32 phys_base_ptr: 0xc0000000 Bits_per_pixel not 32 bit colour Checking Mode Number: 0x168 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 4096 u16 x_resolution: 1024 u16 y_resolution: 600 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 32 u32 phys_base_ptr: 0xc0000000 Panel has no EDID match for this mode! Checking Mode Number: 0x169 Mode not supported Checking Mode Number: 0x16a Mode not supported Checking Mode Number: 0x16b Mode not supported Checking Mode Number: 0x16c Mode not supported Checking Mode Number: 0x16d Mode not supported Checking Mode Number: 0x16e Mode not supported Checking Mode Number: 0x16f Mode not supported Checking Mode Number: 0x170 Mode not supported Checking Mode Number: 0x171 Mode not supported Checking Mode Number: 0x13c Mode not supported Checking Mode Number: 0x14d Mode not supported Checking Mode Number: 0x15c Mode not supported Checking Mode Number: 0x13a Mode not supported Checking Mode Number: 0x14b Mode not supported Checking Mode Number: 0x15a Mode not supported Checking Mode Number: 0x107 Mode not supported Checking Mode Number: 0x11a Mode not supported Checking Mode Number: 0x11b Mode not supported Checking Mode Number: 0x105 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 1024 u16 x_resolution: 1024 u16 y_resolution: 768 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 8 u32 phys_base_ptr: 0xc0000000 Bits_per_pixel not 32 bit colour Checking Mode Number: 0x117 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 2048 u16 x_resolution: 1024 u16 y_resolution: 768 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 16 u32 phys_base_ptr: 0xc0000000 Bits_per_pixel not 32 bit colour Checking Mode Number: 0x118 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 4096 u16 x_resolution: 1024 u16 y_resolution: 768 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 32 u32 phys_base_ptr: 0xc0000000 Found Panel EDID mode match! Better Mode Match, Old = 0x0, New = 0x4118 Checking Mode Number: 0x112 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 2560 u16 x_resolution: 640 u16 y_resolution: 480 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 32 u32 phys_base_ptr: 0xc0000000 Panel has no EDID match for this mode! Checking Mode Number: 0x114 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 1600 u16 x_resolution: 800 u16 y_resolution: 600 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 16 u32 phys_base_ptr: 0xc0000000 Bits_per_pixel not 32 bit colour Checking Mode Number: 0x115 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 3200 u16 x_resolution: 800 u16 y_resolution: 600 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 32 u32 phys_base_ptr: 0xc0000000 Panel has no EDID match for this mode! Checking Mode Number: 0x101 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 640 u16 x_resolution: 640 u16 y_resolution: 480 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 8 u32 phys_base_ptr: 0xc0000000 Bits_per_pixel not 32 bit colour Checking Mode Number: 0x103 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 832 u16 x_resolution: 800 u16 y_resolution: 600 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 8 u32 phys_base_ptr: 0xc0000000 Bits_per_pixel not 32 bit colour Checking Mode Number: 0x111 Mode supported u16 mode_att: 0x9b u8 win_a_att: 0x7 u8 win_b_att: 0x0 u16 win_gran: 0x40 u16 win_size: 0x40 u16 win_a_seg: 0xa000 u16 win_b_seg: 0x0 u32 win_func_ptr: 0xc000816a u16 bytes_per_scanline: 1280 u16 x_resolution: 640 u16 y_resolution: 480 u8 x_charsize: 8 u8 y_charsize: 16 u8 number_of_planes: 1 u8 bits_per_pixel: 16 u32 phys_base_ptr: 0xc0000000 Bits_per_pixel not 32 bit colour Configuring Grapics Controller for EDID Best Fit Mode 0x4118 u16 x_resolution: 1024 u16 y_resolution: 768 **** Configured VBE: resolution: 1024x768@32 ***** Setting VESA mode 0x4118 via INT10h Suitable Mode determined - Setting VESA Mode now! VGA Option ROM was run PCI: 00:02.0 init 2311918 usecs PCI: 00:12.0 init PCI: 00:12.0 init 1848 usecs PCI: 00:13.0 init PCI: 00:13.0 init 1848 usecs PCI: 00:14.0 init PCI: 00:14.0 init 1848 usecs PCI: 00:18.0 init PCI: 00:18.0 init 1848 usecs PCI: 00:18.1 init PCI: 00:18.1 init 1847 usecs PCI: 00:18.2 init PCI: 00:18.2 init 1847 usecs PCI: 00:18.3 init PCI: 00:18.3 init 1848 usecs PCI: 00:18.4 init PCI: 00:18.4 init 1848 usecs PCI: 00:18.5 init PCI: 00:18.5 init 1848 usecs PCI: 00:18.6 init PCI: 00:18.6 init 1848 usecs PCI: 00:18.7 init PCI: 00:18.7 init 1848 usecs PCI: 00:1b.0 init PCI: 00:1b.0 init 1848 usecs PCI: 00:1e.0 init PCI: 00:1e.0 init 1848 usecs PCI: 00:1e.3 init PCI: 00:1e.3 init 1848 usecs PCI: 00:1e.4 init PCI: 00:1e.4 init 1848 usecs PCI: 00:1e.5 init PCI: 00:1e.5 init 1848 usecs PCI: 00:1f.0 init soc: southcluster_init Southbridge APIC ID = 2 Dumping IOAPIC registers reg 0x0000: 0x02000000 reg 0x0001: 0x00560020 reg 0x0002: 0x00560020 Start writing IRQ assignments PIRQ A B C D E F G H IRQ 4 5 7 10 11 12 14 15 PIRQ[A-H] routed to each INT_PIN[A-D] Dev INTA (IRQ) INTB (IRQ) INTC (IRQ) INTD (IRQ) 16: D (10) E (11) F (12) G (14) 17: B (5) A (4) A (4) A (4) 18: C (7) A (4) A (4) A (4) 19: D (10) A (4) A (4) A (4) 20: E (11) A (4) A (4) A (4) 21: F (12) A (4) A (4) A (4) 23: F (12) A (4) A (4) A (4) 24: B (5) A (4) D (10) C (7) 26: F (12) A (4) A (4) A (4) 27: G (14) A (4) A (4) A (4) 28: A (4) B (5) C (7) D (10) 29: D (10) A (4) A (4) A (4) 30: B (5) D (10) E (11) F (12) 31: H (15) G (14) B (5) C (7) Finished writing IRQ assignments PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:02.00 using PIN A Warning: PCI Device 2 does not have an IRQ entry, skipping it PCI IRQ: Found device 0:12.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : C INT_LINE : 0x2F (IRQ 47) PCI IRQ: Found device 0:13.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : D INT_LINE : 0xA (IRQ 10) PCI IRQ: Found device 0:14.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : E INT_LINE : 0x17 (IRQ 23) PCI IRQ: Found device 0:18.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : B INT_LINE : 0x2B (IRQ 43) PCI IRQ: Found device 0:18.01 using PIN C INT_PIN : 3 (PIN C) PIRQ : D INT_LINE : 0x20 (IRQ 32) PCI IRQ: Found device 0:18.02 using PIN D INT_PIN : 4 (PIN D) PIRQ : C INT_LINE : 0x21 (IRQ 33) PCI IRQ: Found device 0:18.03 using PIN B INT_PIN : 2 (PIN B) PIRQ : A INT_LINE : 0x22 (IRQ 34) PCI IRQ: Found device 0:18.04 using PIN A INT_PIN : 1 (PIN A) PIRQ : B INT_LINE : 0x23 (IRQ 35) PCI IRQ: Found device 0:18.05 using PIN C INT_PIN : 3 (PIN C) PIRQ : D INT_LINE : 0x24 (IRQ 36) PCI IRQ: Found device 0:18.06 using PIN D INT_PIN : 4 (PIN D) PIRQ : C INT_LINE : 0x25 (IRQ 37) PCI IRQ: Found device 0:18.07 using PIN B INT_PIN : 2 (PIN B) PIRQ : A INT_LINE : 0x26 (IRQ 38) PCI IRQ: Found device 0:1B.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : G INT_LINE : 0x16 (IRQ 22) PCI IRQ: Found device 0:1C.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : A INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:1C.01 using PIN B INT_PIN : 2 (PIN B) PIRQ : B INT_LINE : 0x5 (IRQ 5) PCI IRQ: Found device 0:1C.02 using PIN C INT_PIN : 3 (PIN C) PIRQ : C INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:1C.03 using PIN D INT_PIN : 4 (PIN D) PIRQ : D INT_LINE : 0xA (IRQ 10) PCI IRQ: Found device 0:1E.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : B INT_LINE : 0x2A (IRQ 42) PCI IRQ: Found device 0:1E.03 using PIN C INT_PIN : 3 (PIN C) PIRQ : E INT_LINE : 0x27 (IRQ 39) PCI IRQ: Found device 0:1E.04 using PIN D INT_PIN : 4 (PIN D) PIRQ : F INT_LINE : 0x28 (IRQ 40) PCI IRQ: Found device 0:1E.05 using PIN B INT_PIN : 2 (PIN B) PIRQ : D INT_LINE : 0x29 (IRQ 41) PCI IRQ: Found device 0:1F.03 using PIN B INT_PIN : 2 (PIN B) PIRQ : G INT_LINE : 0xE (IRQ 14) PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:1Ch.01h INT_PIN : 1 (PIN A) Swizzled to : 1 (PIN A) PIRQ : A INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 3:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:1Ch.02h INT_PIN : 1 (PIN A) Swizzled to : 1 (PIN A) PIRQ : A INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments PCI: 00:1f.0 init 372220 usecs PCI: 00:1f.3 init PCI: 00:1f.3 init 1848 usecs PCI: 02:00.0 init PCI: 02:00.0 init 1848 usecs PCI: 03:00.0 init PCI: 03:00.0 init 1848 usecs Devices initialized Show all devs...After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:15.0: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 PCI: 00:1a.0: enabled 0 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: 00:1c.2: enabled 1 PCI: 00:1c.3: enabled 1 PCI: 00:1d.0: enabled 0 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 0 PCI: 00:1e.3: enabled 1 PCI: 00:1e.4: enabled 1 PCI: 00:1e.5: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 02:00.0: enabled 1 PCI: 03:00.0: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 2936180 exit 0 Finalize devices... DOMAIN: 0000 final Devices finalized Update pci root memory resource range ... PCI: 00:00, device:80860f00 PCI: 02:00, device:80860f31 res->base = d0000000, res->size = 400000, res->limit = dfffffff res->base = c0000000, res->size = 10000000, res->limit = dfffffff PCI: 03:00, device:00000000 PCI: 10:00, device:00000000 PCI: 11:00, device:00000000 PCI: 12:00, device:80860f16 res->base = d071c000, res->size = 1000, res->limit = dfffffff res->base = d071d000, res->size = 1000, res->limit = dfffffff PCI: 13:00, device:80860f23 res->base = d0734000, res->size = 800, res->limit = dfffffff PCI: 14:00, device:80860f35 res->base = d0700000, res->size = 10000, res->limit = dfffffff PCI: 15:00, device:00000000 PCI: 16:00, device:00000000 PCI: 17:00, device:00000000 PCI: 18:00, device:80860f40 res->base = d0710000, res->size = 4000, res->limit = dfffffff res->base = d071e000, res->size = 1000, res->limit = dfffffff PCI: 18:01, device:80860f41 res->base = d071f000, res->size = 1000, res->limit = dfffffff res->base = d0720000, res->size = 1000, res->limit = dfffffff PCI: 18:02, device:80860f42 res->base = d0721000, res->size = 1000, res->limit = dfffffff res->base = d0722000, res->size = 1000, res->limit = dfffffff PCI: 18:03, device:80860f43 res->base = d0723000, res->size = 1000, res->limit = dfffffff res->base = d0724000, res->size = 1000, res->limit = dfffffff PCI: 18:04, device:80860f44 res->base = d0725000, res->size = 1000, res->limit = dfffffff res->base = d0726000, res->size = 1000, res->limit = dfffffff PCI: 18:05, device:80860f45 res->base = d0727000, res->size = 1000, res->limit = dfffffff res->base = d0728000, res->size = 1000, res->limit = dfffffff PCI: 18:06, device:80860f46 res->base = d0729000, res->size = 1000, res->limit = dfffffff res->base = d072a000, res->size = 1000, res->limit = dfffffff PCI: 18:07, device:80860f47 res->base = d072b000, res->size = 1000, res->limit = dfffffff res->base = d072c000, res->size = 1000, res->limit = dfffffff PCI: 1a:00, device:00000000 PCI: 1b:00, device:80860f04 res->base = d0714000, res->size = 4000, res->limit = dfffffff PCI: 1c:00, device:80860f48 PCI: 1c:01, device:80860f4a res->base = d0400000, res->size = 200000, res->limit = dfffffff PCI: 1c:02, device:80860f4c res->base = d0600000, res->size = 100000, res->limit = dfffffff PCI: 1c:03, device:80860f4e PCI: 1d:00, device:00000000 PCI: 1e:00, device:80860f06 res->base = d0718000, res->size = 4000, res->limit = dfffffff res->base = d072d000, res->size = 1000, res->limit = dfffffff PCI: 1e:01, device:00000000 PCI: 1e:02, device:00000000 PCI: 1e:03, device:80860f0a res->base = d072e000, res->size = 1000, res->limit = dfffffff res->base = d072f000, res->size = 1000, res->limit = dfffffff PCI: 1e:04, device:80860f0c res->base = d0730000, res->size = 1000, res->limit = dfffffff res->base = d0731000, res->size = 1000, res->limit = dfffffff PCI: 1e:05, device:80860f0e res->base = d0732000, res->size = 1000, res->limit = dfffffff res->base = d0733000, res->size = 1000, res->limit = dfffffff PCI: 1f:00, device:80860f1c PCI: 1f:03, device:80860f12 res->base = d0734800, res->size = 20, res->limit = dfffffff PCI: 00:00, device:168c003e res->base = d0400000, res->size = 200000, res->limit = dfffffff PCI: 00:00, device:80861539 res->base = d0600000, res->size = 20000, res->limit = dfffffff res->base = d0620000, res->size = 4000, res->limit = dfffffff pci range low=c0000000, high=d0734820, limit=dfffffff Remaining PCI range for ACPI: start=d0741000, end=dfffffff config->LpssSioEnablePciMode = 0 dev: devfn = 0x0:0, enabled=1 dev: devfn = 0x2:0, enabled=1 dev: devfn = 0x3:0, enabled=0 dev: devfn = 0x10:0, enabled=0 dev: devfn = 0x11:0, enabled=0 dev: devfn = 0x12:0, enabled=1 dev: devfn = 0x13:0, enabled=1 dev: devfn = 0x14:0, enabled=1 dev: devfn = 0x15:0, enabled=0 dev: devfn = 0x16:0, enabled=0 dev: devfn = 0x17:0, enabled=0 dev: devfn = 0x18:0, enabled=1 Org address = 0xd0710000, size = 0x4000, limit = 0xdfffffff New address = 0xd0741000, size = 0x4000, limit = 0xdfffffff Org address = 0xd071e000, size = 0x1000, limit = 0xdfffffff New address = 0xd0745000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd0741000, size=0x4000 update bar1 nvs=0xd0745000, size=0x1000 dev: devfn = 0x18:1, enabled=1 Org address = 0xd071f000, size = 0x1000, limit = 0xdfffffff New address = 0xd0746000, size = 0x1000, limit = 0xdfffffff Org address = 0xd0720000, size = 0x1000, limit = 0xdfffffff New address = 0xd0747000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd0746000, size=0x1000 update bar1 nvs=0xd0747000, size=0x1000 dev: devfn = 0x18:2, enabled=1 Org address = 0xd0721000, size = 0x1000, limit = 0xdfffffff New address = 0xd0748000, size = 0x1000, limit = 0xdfffffff Org address = 0xd0722000, size = 0x1000, limit = 0xdfffffff New address = 0xd0749000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd0748000, size=0x1000 update bar1 nvs=0xd0749000, size=0x1000 dev: devfn = 0x18:3, enabled=1 Org address = 0xd0723000, size = 0x1000, limit = 0xdfffffff New address = 0xd074a000, size = 0x1000, limit = 0xdfffffff Org address = 0xd0724000, size = 0x1000, limit = 0xdfffffff New address = 0xd074b000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd074a000, size=0x1000 update bar1 nvs=0xd074b000, size=0x1000 dev: devfn = 0x18:4, enabled=1 Org address = 0xd0725000, size = 0x1000, limit = 0xdfffffff New address = 0xd074c000, size = 0x1000, limit = 0xdfffffff Org address = 0xd0726000, size = 0x1000, limit = 0xdfffffff New address = 0xd074d000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd074c000, size=0x1000 update bar1 nvs=0xd074d000, size=0x1000 dev: devfn = 0x18:5, enabled=1 Org address = 0xd0727000, size = 0x1000, limit = 0xdfffffff New address = 0xd074e000, size = 0x1000, limit = 0xdfffffff Org address = 0xd0728000, size = 0x1000, limit = 0xdfffffff New address = 0xd074f000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd074e000, size=0x1000 update bar1 nvs=0xd074f000, size=0x1000 dev: devfn = 0x18:6, enabled=1 Org address = 0xd0729000, size = 0x1000, limit = 0xdfffffff New address = 0xd0750000, size = 0x1000, limit = 0xdfffffff Org address = 0xd072a000, size = 0x1000, limit = 0xdfffffff New address = 0xd0751000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd0750000, size=0x1000 update bar1 nvs=0xd0751000, size=0x1000 dev: devfn = 0x18:7, enabled=1 Org address = 0xd072b000, size = 0x1000, limit = 0xdfffffff New address = 0xd0752000, size = 0x1000, limit = 0xdfffffff Org address = 0xd072c000, size = 0x1000, limit = 0xdfffffff New address = 0xd0753000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd0752000, size=0x1000 update bar1 nvs=0xd0753000, size=0x1000 dev: devfn = 0x1a:0, enabled=0 dev: devfn = 0x1b:0, enabled=1 dev: devfn = 0x1c:0, enabled=1 dev: devfn = 0x1c:1, enabled=1 dev: devfn = 0x1c:2, enabled=1 dev: devfn = 0x1c:3, enabled=1 dev: devfn = 0x1d:0, enabled=0 dev: devfn = 0x1e:0, enabled=1 Org address = 0xd0718000, size = 0x4000, limit = 0xdfffffff New address = 0xd0754000, size = 0x4000, limit = 0xdfffffff Org address = 0xd072d000, size = 0x1000, limit = 0xdfffffff New address = 0xd0758000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd0754000, size=0x4000 update bar1 nvs=0xd0758000, size=0x1000 dev: devfn = 0x1e:1, enabled=0 dev: devfn = 0x1e:2, enabled=0 dev: devfn = 0x1e:3, enabled=1 Org address = 0xd072e000, size = 0x1000, limit = 0xdfffffff New address = 0xd0759000, size = 0x1000, limit = 0xdfffffff Org address = 0xd072f000, size = 0x1000, limit = 0xdfffffff New address = 0xd075a000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd0759000, size=0x1000 update bar1 nvs=0xd075a000, size=0x1000 dev: devfn = 0x1e:4, enabled=1 Org address = 0xd0730000, size = 0x1000, limit = 0xdfffffff New address = 0xd075b000, size = 0x1000, limit = 0xdfffffff Org address = 0xd0731000, size = 0x1000, limit = 0xdfffffff New address = 0xd075c000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd075b000, size=0x1000 update bar1 nvs=0xd075c000, size=0x1000 dev: devfn = 0x1e:5, enabled=1 Org address = 0xd0732000, size = 0x1000, limit = 0xdfffffff New address = 0xd075d000, size = 0x1000, limit = 0xdfffffff Org address = 0xd0733000, size = 0x1000, limit = 0xdfffffff New address = 0xd075e000, size = 0x1000, limit = 0xdfffffff update bar0 nvs=0xd075d000, size=0x1000 update bar1 nvs=0xd075e000, size=0x1000 dev: devfn = 0x1f:0, enabled=1 dev: devfn = 0x1f:3, enabled=1 dev: devfn = 0x0:0, enabled=1 dev: devfn = 0x0:0, enabled=1 BS: BS_POST_DEVICE times (us): entry 0 run 5836 exit 867844 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0 === FSP HOB Data Structure === FSP Hoblistptr: 0x7b620000 HOB 0x7b620000 is an EFI_HOB_TYPE_HANDOFF (type 0x1) HOB 0x7b620038 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7b6200f0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7b6201e8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7b621860 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x0 with length 0xa0000 HOB 0x7b621890 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07 at location 0xa0000 with length 0x60000 HOB 0x7b6218c0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x100000 with length 0x7b500000 HOB 0x7b6218f0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07 at location 0x7b600000 with length 0x700000 HOB 0x7b621920 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x407 at location 0x7bd00000 with length 0x100000 HOB 0x7b621950 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x407 at location 0x7be00000 with length 0x4200000 HOB 0x7b621980 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b600000 with length 0x20000 HOB 0x7b6219b0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7ff000 with length 0x1000 HOB 0x7b6219e0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7f8000 with length 0x7000 HOB 0x7b621a10 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7b625a28 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7f5000 with length 0x3000 HOB 0x7b625a58 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7b625c08 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7f1000 with length 0x4000 HOB 0x7b625c38 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7ef000 with length 0x2000 HOB 0x7b625c68 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7ee000 with length 0x1000 HOB 0x7b625c98 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7ea000 with length 0x4000 HOB 0x7b625cc8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7e6000 with length 0x4000 HOB 0x7b625cf8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7e3000 with length 0x3000 HOB 0x7b625d28 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7df000 with length 0x4000 HOB 0x7b625d58 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7d8000 with length 0x7000 HOB 0x7b625d88 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7d2000 with length 0x6000 HOB 0x7b625db8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7ce000 with length 0x4000 HOB 0x7b625de8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7ca000 with length 0x4000 HOB 0x7b625e18 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7c7000 with length 0x3000 HOB 0x7b625e48 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7c3000 with length 0x4000 HOB 0x7b625e78 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7b4000 with length 0xf000 HOB 0x7b625ea8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7a6000 with length 0xe000 HOB 0x7b625ed8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7a2000 with length 0x4000 HOB 0x7b625f08 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b7a0000 with length 0x2000 HOB 0x7b625f38 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b79f000 with length 0x1000 HOB 0x7b625f68 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b79b000 with length 0x4000 HOB 0x7b625f98 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b797000 with length 0x4000 HOB 0x7b625fc8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b794000 with length 0x3000 HOB 0x7b625ff8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b790000 with length 0x4000 HOB 0x7b626028 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b78b000 with length 0x5000 HOB 0x7b626058 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b787000 with length 0x4000 HOB 0x7b626088 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b6260a0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b6260e0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b6260f8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b626140 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b626150 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b626168 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b626178 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b626188 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b626198 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b6263a0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7b777000 with length 0x10000 HOB 0x7b6263d0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7b6264f0 is an EFI_HOB_TYPE_END_OF_HOB_LIST (type 0xffff) === End of FSP HOB Data Structure === Memory Configure Data Hob is not present Not updating MRC data in flash. ACPI: Writing ACPI tables at 7b5ef000. ACPI: * FACS @ 7b5ef210 Length 40ACPI: * DSDT @ 7b5ef250 Length 3009SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * FADT @ 7b5f2260 Length f4ACPI: added table 2/32, length now 44 ACPI: * HPET @ 7b5f2360 Length 38 ACPI: added table 3/32, length now 48 ACPI: * MADT @ 7b5f23a0 Length 54 ACPI: added table 4/32, length now 52 ACPI: * MCFG @ 7b5f2400 Length 3c ACPI: * CSRT acpi_fill_csrt: start current = 7b5f2464 acpi_fill_csrt, end current = 7b5f258c Initialize CSRT End, LpssDMA2Bar0=d0754000, LpssDMA1Bar0=d0741000 ACPI: added table 5/32, length now 56 ACPI: * IGD OpRegion GET_VBIOS: aa55 8086 0 0 3 ... VBIOS found at 000c0000 Set GFX OpRegion at 0x7b5f2590 ACPI: Patching up global NVS in DSDT at offset 0x00eb -> 7b5fb000 ACPI Updated DSDT @ 7b5ef250 Length 3009 Turbo is unavailable PSS: 1466MHz power 0 control 0xb3a status 0xb3a PSS: 1333MHz power 0 control 0xa38 status 0xa38 PSS: 1199MHz power 0 control 0x936 status 0x936 PSS: 1066MHz power 0 control 0x833 status 0x833 PSS: 933MHz power 0 control 0x731 status 0x731 PSS: 799MHz power 0 control 0x62e status 0x62e PSS: 666MHz power 0 control 0x52c status 0x52c PSS: 533MHz power 0 control 0x429 status 0x429 ACPI: added table 6/32, length now 60 ACPI: * SSDT @ 7b5f4740 Length 392 ACPI: * SSDT2 not generated. current = 7b5f4ae0 ACPI: done. ACPI tables: 23264 bytes. smbios_write_tables: 7b5ec000 Root Device (Intel Bayley Bay CRB) CPU_CLUSTER: 0 (Intel BayTrail SoC) APIC: 00 (Intel BayTrail SoC) DOMAIN: 0000 (Intel BayTrail SoC) PCI: 00:00.0 (Intel BayTrail SoC) PCI: 00:02.0 (Intel BayTrail SoC) PCI: 00:03.0 (Intel BayTrail SoC) PCI: 00:10.0 (Intel BayTrail SoC) PCI: 00:11.0 (Intel BayTrail SoC) PCI: 00:12.0 (Intel BayTrail SoC) PCI: 00:13.0 (Intel BayTrail SoC) PCI: 00:14.0 (Intel BayTrail SoC) PCI: 00:15.0 (Intel BayTrail SoC) PCI: 00:16.0 (Intel BayTrail SoC) PCI: 00:17.0 (Intel BayTrail SoC) PCI: 00:18.0 (Intel BayTrail SoC) PCI: 00:18.1 (Intel BayTrail SoC) PCI: 00:18.2 (Intel BayTrail SoC) PCI: 00:18.3 (Intel BayTrail SoC) PCI: 00:18.4 (Intel BayTrail SoC) PCI: 00:18.5 (Intel BayTrail SoC) PCI: 00:18.6 (Intel BayTrail SoC) PCI: 00:18.7 (Intel BayTrail SoC) PCI: 00:1a.0 (Intel BayTrail SoC) PCI: 00:1b.0 (Intel BayTrail SoC) PCI: 00:1c.0 (Intel BayTrail SoC) PCI: 00:1c.1 (Intel BayTrail SoC) PCI: 00:1c.2 (Intel BayTrail SoC) PCI: 00:1c.3 (Intel BayTrail SoC) PCI: 00:1d.0 (Intel BayTrail SoC) PCI: 00:1e.0 (Intel BayTrail SoC) PCI: 00:1e.1 (Intel BayTrail SoC) PCI: 00:1e.2 (Intel BayTrail SoC) PCI: 00:1e.3 (Intel BayTrail SoC) PCI: 00:1e.4 (Intel BayTrail SoC) PCI: 00:1e.5 (Intel BayTrail SoC) PCI: 00:1f.0 (Intel BayTrail SoC) PCI: 00:1f.3 (Intel BayTrail SoC) PCI: 02:00.0 (unknown) PCI: 03:00.0 (unknown) SMBIOS tables: 364 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4490 Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0x7b4e4000 rom_table_end = 0x7b4e4000 ... aligned to 0x7b4f0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007b4e3fff: RAM 4. 000000007b4e4000-000000007b5fffff: CONFIGURATION TABLES 5. 000000007b600000-000000007fffffff: RESERVED 6. 00000000e0000000-00000000efffffff: RESERVED 7. 00000000feb00000-00000000fec00fff: RESERVED 8. 00000000fed01000-00000000fed01fff: RESERVED 9. 00000000fed03000-00000000fed03fff: RESERVED 10. 00000000fed05000-00000000fed05fff: RESERVED 11. 00000000fed08000-00000000fed08fff: RESERVED 12. 00000000fed0c000-00000000fed0ffff: RESERVED 13. 00000000fed1c000-00000000fed1cfff: RESERVED 14. 00000000fee00000-00000000fee00fff: RESERVED 15. 00000000fef00000-00000000feffffff: RESERVED 16. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 7b4e4000, 0x258 bytes, checksum e181 coreboot table: 624 bytes. CBMEM ROOT 0. 7b5ff000 00001000 484f4221 1. 7b5fe000 00001000 ROMSTAGE 2. 7b5fd000 00001000 GDT 3. 7b5fc000 00001000 ACPI GNVS 4. 7b5fb000 00001000 ACPI 5. 7b5ef000 0000c000 4f444749 6. 7b5ee000 00001000 GNVS PTR 7. 7b5ed000 00001000 SMBIOS 8. 7b5ec000 00001000 ACPI RESUME 9. 7b4ec000 00100000 COREBOOT 10. 7b4e4000 00008000 FSP Got Notification. Notification Value : 0x00000020 FSP Post PCI Enumeration ... Install PPI: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7B7A68ED PchReadyToBootEvent() Start PciERWORegInit() Start PciERWORegInit() End Endpoint Device 0 Capability ASPM: 3 Calculate Endpoint Device 0 Aspm Value: 3 Program Endpoint Device 0 Aspm Value: 0 Endpoint Device 0 Capability ASPM: 3 Calculate Endpoint Device 0 Aspm Value: 3 Program Endpoint Device 0 Aspm Value: 0 PchReadyToBootEvent() End FSP Notification Handler Returns : 0x00000000 BS: BS_WRITE_TABLES times (us): entry 647922 run 493673 exit 0 CBFS: located payload @ ffe28378, 745744 bytes. Loading segment from rom address 0xffe28378 code (compression=1) New segment dstaddr 0x800000 memsize 0x400000 srcaddr 0xffe283b0 filesize 0xb60d8 (cleaned up) New segment addr 0x800000 size 0x400000 offset 0xffe283b0 filesize 0xb60d8 Loading segment from rom address 0xffe28394 Entry Point 0x008007a0 Bounce Buffer at 7b455000, 581744 bytes Loading Segment: addr: 0x0000000000800000 memsz: 0x0000000000400000 filesz: 0x00000000000b60d8 lb: [0x0000000000100000, 0x0000000000147038) Post relocation: addr: 0x0000000000800000 memsz: 0x0000000000400000 filesz: 0x00000000000b60d8 using LZMA [ 0x00800000, 00c00000, 0x00c00000) <- ffe283b0 dest 00800000, end 00c00000, bouncebuffer 7b455000 Loaded segments FSP Got Notification. Notification Value : 0x00000040 FSP Ready To Boot ... Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7B7A6B40 PchInitExitBootCallback() Start LockPciDevCap() BusNumber = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x0,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE0000000 LockPciDevCap() StatusReg = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x2,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE0010000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0xD0 LockPciDevCap() While CAPBILITY = 0x9001 LockPciDevCap() While CapId = 0x90 LockPciDevCap() While CAPBILITY = 0xB005 LockPciDevCap() While CapId = 0xB0 LockPciDevCap() While CAPBILITY = 0x9 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x12,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE0090000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x13,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE0098000 LockPciDevCap() StatusReg = 0x2B0 LockPciDevCap() StatusReg = 0x2B0 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x7005 LockPciDevCap() While CapId = 0x70 LockPciDevCap() While CAPBILITY = 0xA801 LockPciDevCap() While CapId = 0xA8 LockPciDevCap() While CAPBILITY = 0x12 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x14,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE00A0000 LockPciDevCap() StatusReg = 0x290 LockPciDevCap() StatusReg = 0x290 LockPciDevCap() CapId = 0x70 LockPciDevCap() While CAPBILITY = 0x8001 LockPciDevCap() While CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x5 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x18,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE00C0000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x18,Func = 0x1 LockPciDevCap() PciEAddressBase = 0xE00C1000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x18,Func = 0x2 LockPciDevCap() PciEAddressBase = 0xE00C2000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x18,Func = 0x3 LockPciDevCap() PciEAddressBase = 0xE00C3000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x18,Func = 0x4 LockPciDevCap() PciEAddressBase = 0xE00C4000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x18,Func = 0x5 LockPciDevCap() PciEAddressBase = 0xE00C5000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x18,Func = 0x6 LockPciDevCap() PciEAddressBase = 0xE00C6000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x18,Func = 0x7 LockPciDevCap() PciEAddressBase = 0xE00C7000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1B,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE00D8000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x50 LockPciDevCap() While CAPBILITY = 0x6001 LockPciDevCap() While CapId = 0x60 LockPciDevCap() While CAPBILITY = 0x5 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1C,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE00E0000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x40 LockPciDevCap() While CAPBILITY = 0x8010 LockPciDevCap() While CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x9005 LockPciDevCap() While CapId = 0x90 LockPciDevCap() While CAPBILITY = 0xA00D LockPciDevCap() While CapId = 0xA0 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1C,Func = 0x1 LockPciDevCap() PciEAddressBase = 0xE00E1000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x40 LockPciDevCap() While CAPBILITY = 0x8010 LockPciDevCap() While CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x9005 LockPciDevCap() While CapId = 0x90 LockPciDevCap() While CAPBILITY = 0xA00D LockPciDevCap() While CapId = 0xA0 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1C,Func = 0x2 LockPciDevCap() PciEAddressBase = 0xE00E2000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x40 LockPciDevCap() While CAPBILITY = 0x8010 LockPciDevCap() While CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x9005 LockPciDevCap() While CapId = 0x90 LockPciDevCap() While CAPBILITY = 0xA00D LockPciDevCap() While CapId = 0xA0 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1C,Func = 0x3 LockPciDevCap() PciEAddressBase = 0xE00E3000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x40 LockPciDevCap() While CAPBILITY = 0x8010 LockPciDevCap() While CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x9005 LockPciDevCap() While CapId = 0x90 LockPciDevCap() While CAPBILITY = 0xA00D LockPciDevCap() While CapId = 0xA0 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1E,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE00F0000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1E,Func = 0x3 LockPciDevCap() PciEAddressBase = 0xE00F3000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1E,Func = 0x4 LockPciDevCap() PciEAddressBase = 0xE00F4000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1E,Func = 0x5 LockPciDevCap() PciEAddressBase = 0xE00F5000 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() StatusReg = 0x10 LockPciDevCap() CapId = 0x80 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1F,Func = 0x0 LockPciDevCap() PciEAddressBase = 0xE00F8000 LockPciDevCap() StatusReg = 0x210 LockPciDevCap() StatusReg = 0x210 LockPciDevCap() CapId = 0xE0 LockPciDevCap() While CAPBILITY = 0x9 LockPciDevCap() While CapId = 0x0 LockPciDevCap() Bus = 0x0,Dev = 0x1F,Func = 0x3 LockPciDevCap() PciEAddressBase = 0xE00FB000 LockPciDevCap() StatusReg = 0x290 LockPciDevCap() StatusReg = 0x290 LockPciDevCap() CapId = 0x50 LockPciDevCap() While CAPBILITY = 0x1 LockPciDevCap() While CapId = 0x0 ConfigureMiscAtBoot() Start ConfigureMiscAtBoot() End ConfigureLpeAtBoot() Start ConfigureLpeAtBoot() End ConfigureOtgAtBoot() Start ConfigureOtgAtBoot() End ConfigureLpssAtBoot() Start Switching LPSS1 DMA into ACPI Mode. Switching LPSS2 DMA into ACPI Mode. Switching LPSS2 I2C 0 into ACPI Mode. Switching LPSS2 I2C 1 into ACPI Mode. Switching LPSS2 I2C 2 into ACPI Mode. Switching LPSS2 I2C 3 into ACPI Mode. Switching LPSS2 I2C 4 into ACPI Mode. Switching LPSS2 I2C 5 into ACPI Mode. Switching LPSS2 I2C 6 into ACPI Mode. Switching LPSS1 HS-UART 0 into ACPI Mode. Switching LPSS1 HS-UART 1 into ACPI Mode. Switching LPSS1 SPI into ACPI Mode. ConfigureLpssAtBoot() End ConfigureSccAtBoot() Start Using eMMC 4.5 Overwrite the nslew/pslew -> 0 ConfigureSccAtBoot() End ConfigureXhciAtBoot() Start ConfigureXhciAtBoot() End PchInitExitBootCallback() End Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7B7C75A7 Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7B794804 MP ReadyToBootEvent() FSP Notification Handler Returns : 0x00000000 ============= PEIM FSP is Completed ============= BS: BS_PAYLOAD_LOAD times (us): entry 0 run 1322914 exit 0 Jumping to boot code at 008007a0 CPU0: stack: 00142000 - 00143000, lowest used address 00142aec, stack used: 1300 bytes entry = 0x008007a0 lb_start = 0x00100000 lb_size = 0x00047038 buffer = 0x7b455000 [=3h[=3h[=3h[=3h[=3h[=3hSystem BootOrder not found. Initializing defaults. Creating boot entry "Boot0002" with label "ubuntu" for file "\EFI\ubuntu\shimx64.efi"