On 3/13/20 11:23 AM, Angel Pons wrote: > Hi, > > On Thu, Mar 12, 2020 at 11:07 AM Michal Zygowski > <[email protected]> wrote: >> >> Hi, >> >> it may also be a Cedarview chipset. According to my knowledge there is >> no support for Cedarview chipset in coreboot. However coreboot has >> slightly older (1 year older) chipset support - Pineview. > > Pineview is very different, though. Memory initialization for Pineview > resembles that of Eaglelake (src/northbridge/intel/x4x). Although it > only has one memory channel, the registers in MCHBAR are very similar. > > On the other hand, Cedarview's internal architecture differs radically > from Pineview, and it is actually more like Bay Trail. Both use the > IOSF architecture, and memory is initialized by interacting with > various "units" inside the chip. > > About the southbridge, I don't know if Cedarview can use NM10 (found > on Pineview) or if it must use an EG20T PCH: > https://ark.intel.com/content/www/us/en/ark/products/52501/intel-platform-controller-hub-eg20t.html
Hi, isn't Cedarview a processor code name and Cedar Trail platform code name? This presentation mix both: https://manualzz.com/doc/26041007/cedar-trail-platform-bios-session Interesting slide is 21, this lead me to pre-FSP time when BLDK was used and I found this: https://www.intel.pl/content/dam/www/public/us/en/documents/guides/cedar-trail-bldk-get-started-guide.pdf Probably only companies that have CNDA with Intel can still obtain those, but who knows maybe it lays on some server somewhere. Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
