Hi Cameron,
I contact you since I am doing the same development as you.
In my company we developed a board based on Leaf-hill CRB from Intel. I am in
the process of making a clean image of the bios and I find the following
problem to see if you can help me.
Complete all the process that you comment having the account the last files of
this year:
Coreboot: V4.9
FSP: Intel MR5 (566285)
IFWI image: "Intel-atome-e3900-soc-ifwi-224-41-release-package" (I think it is
the last one available). Inside it has a ready-to-record image in 8Mb SPI.
Do you know why most of the documents have 8mb images when the CRB that I
have and my mother has 16Mb?
The Flash description is extracted from the image that the CRB originally has
with the tool "ifdtool.c".
it is right?
Well with these elements I configure coreboot using "menuconfig" as you
mentioned in your post, at first I had an error compiling because I did not
choose to use the BLOBS repo that it has in this version.
Is that configuration fine?
Finally, I managed to buid but at the end the following legend appears:
"""
This image contains the following sections that can be manipulated with this
tool:
'SI_DESC' (size 4096, offset 0)
'IFWI' (size 3141632, offset 4096)
'COREBOOT' (CBFS, size 12703744, offset 3147776)
'RECOVERY_MRC_CACHE' (size 65536, offset 15851520)
'RW_MRC_CACHE' (size 65536, offset 15917056)
'RW_VAR_MRC_CACHE' (size 4096, offset 15982592)
'BIOS_UNUSABLE' (size 262144, offset 15986688)
'DEVICE_EXTENSION' (size 520192, offset 16248832)
'UNUSED_HOLE' (size 4096, offset 16773120)
It is possible to perform either the write action or the CBFS add/remove
actions on every section listed above.
To see the image's read-only sections as well, rerun with the -w option.
CBFSPRINT coreboot.rom
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs master header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 34116 none
cpu_microcode_blob.bin 0x8600 microcode 46080 none
fallback/ramstage 0x13a80 stage 76438 none
config 0x26580 raw 304 none
revision 0x26700 raw 673 none
fallback/postcar 0x26a00 stage 16680 none
fallback/dsdt.aml 0x2ab80 raw 5581 none
fallback/payload 0x2c1c0 simple elf 67427 none
payload_config 0x3c980 raw 1637 none
payload_revision 0x3d040 raw 235 none
(empty) 0x3d180 null 12420632 none
bootblock 0xc157c0 bootblock 32768 none
Built intel/leafhill (Leafhill)
Image written successfully to build/cbfs/fallback/ifwi.bin.tmp.
Image does not contain sub-partition OBBP(6).
Sub-partition IBBP(4) entry IBBL replaced from file
build/cbfs/fallback/bootblock.bin.
Image written successfully to build/cbfs/fallback/ifwi.bin.tmp.
W: Written area will abut bottom of target region: any unused space will keep
its current contents
** WARNING **
coreboot has been built without an Intel Firmware Descriptor.
Never write a complete coreboot.rom without an IFD to your
board's flash chip! You can use flashrom's IFD or layout
parameters to flash only to the BIOS region.
"""
To you this warning happens, because of that the .bin is not generated to
download in the SPI memory.
Can you help me with this situation?
Thank you
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