On 10/16/18 9:46 AM, Christian Gmeiner wrote: > Am Mo., 15. Okt. 2018 um 15:26 Uhr schrieb Naresh G. Solanki > <[email protected]>: >> For problem 1, can you give data on where exactly it hangs?, Is it in >> OS or FW ?, Can you provide kernel/coreboot log, port 80 dump when it >> hangs. > > It only hangs If I change the following values: > > mem_cfg->PegDisableSpreadSpectrumClocking = 1; > mem_cfg->PchPmPciePllSsc = 0; > > The 'physical' cause for the hang is also known: PLT_RST# never gets > high again. There are chances > that it does not hang but PCI devices (sata, usb hc, ...) are not > working as expected as the PCe reference clock > is in such a case at around 92 Mhz.
You said earlier that you can dump (but not change) the ICC settings, right? Did you check what settings are made with PchPmPciePllSsc == 0? If FSP ends up enabling it with a value of 0, I could imagine that this is just unexpected / the result undefined. Did you try other values than 0? 1? I guess the value gives a percentage of a percentage; 0.01% down- spread is probably not too bad. And maybe somebody with access to the FSP source can document what it does and if there is a switch (missing) to disabled it ;) Nico -- coreboot mailing list: [email protected] https://mail.coreboot.org/mailman/listinfo/coreboot
