On Sun, Jun 24, 2018 at 11:28:11PM +0200, Rudolf Marek wrote: > Hi, > > Lets do some speculation that some off the shelf DDR memory controller is > used.
Probably. > Maybe it could be same as the RockChip aka Denali High-Speed DDR PHY IP from > Cadence? > It has also some "interrupt status" bits and such and "bstlen" which sounds > same as the few > regs named as the documentation. I haven't compared the register maps, and I'm not familiar with other controllers, this sounds like a good lead. If this is the Denali DDR controller, do you think it would be possible to simply read the initial configuration out of the registers of a booted system? (In any case, that's probably worth trying.) Jonathan Neuschäfer
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