On Thu, Apr 28, 2016 at 1:38 AM, Alexander Böcken <[email protected]> wrote: > Hi community, > > I'm trying to get coreboot running on a Braswell CPU but it hangs when > updating the microcode. I'm stuck in bootblock before CAR and could pin down > the problem to the intel_microcode_load_unlocked function in > src/cpu/intel/microcode.c where coreboot writes the microcode base address to > the IA32_BIOS_UPDT_TRIG register (0x79). > > outb(0xF7, 0x80); > > msr.lo = (unsigned long)m + sizeof(struct microcode); > msr.hi = 0; > wrmsr(0x79, msr); > > outb(0xF8, 0x80); > > The outb calls have been added by me, and F7 is just the last post code I > see, a few seconds before the CPU reboots. It never reaches F8. So I checked > the microcode that I've received from Intel and everything seems fine. The > microcode signature matches the CPUID, the platform flags match, the checksum > correctly yields to zero, and the base address is aligned on a 16-byte > boundary. Some checks are also done by coreboot at runtime. I just can't > figure out what the problem is here. >
What's the disassembly of your bootblock look like? Or if you have a board target I can try and build one myself. > Some more Info: > > $ build/cbfstool build/coreboot.rom print > Performing operation on 'COREBOOT' region... > Name Offset Type Size > cbfs master header 0x0 cbfs header 32 > fallback/romstage 0x80 stage 30660 > fallback/ramstage 0x78c0 stage 63482 > fallback/payload 0x17100 payload 61118 > config 0x26000 raw 439 > revision 0x26200 raw 575 > cmos_layout.bin 0x26480 cmos_layout 1128 > fallback/dsdt.aml 0x26940 raw 17603 > payload_config 0x2ae80 raw 1563 > payload_revision 0x2b500 raw 233 > (empty) 0x2b640 null 248856 > cpu_microcode_blob.bin 0x68280 microcode 68608 > (empty) 0x78f00 null 683928 > fsp.bin 0x11fec0 fsp 296960 > (empty) 0x168700 null 489368 > mrc.cache 0x1dfec0 mrc_cache 65536 > (empty) 0x1eff00 null 63960 > bootblock 0x1ff900 bootblock 1424 > > $ cat ".config" | grep "MICROCODE" > # CONFIG_USES_MICROCODE_HEADER_FILES is not set > CONFIG_CPU_MICROCODE_CBFS_GENERATE=y > # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set > # CONFIG_CPU_MICROCODE_CBFS_NONE is not set > # CONFIG_CPU_MICROCODE_MULTIPLE_FILES is not set > CONFIG_CPU_MICROCODE_CBFS_LEN=0x10C00 > CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFE68400 > # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set > > I really appreciate any hints. > > Alex > > -- > coreboot mailing list: [email protected] > https://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
