* Georg Wicherski <[email protected]> [151019 17:39]: > Hi, > > thanks to Marc Jones' SGD patch for the Auron board > (f3214d02482a4104d7276f06d6b326b2a54c4262), I was able to get my > Auron_Paine up to ramstage. > > Unfortunately, the IGD code in soc/intel/broadwell/ appears to be > somewhat broken. Based off Aaron's guidance on IRC, I've pin-pointed the > issue to be within igd_setup_panel . The first gtt_read there seems to > hang already (BIOS_SPEW log attached). Find my current code with those > debug prints at <http://review.coreboot.org/#/c/11907/2>. FWIW, I've > tested with some commenting-out, etc. that it's any gtt_read that > immediately causes a hang there. Also dumped the gtt_res, small excerpt > from the log: > > --8<-- > igd's gtt_res = { base=e0000000, size=1000000, limit=e0ffffff, > flags=60000201 } > igd_init: waited for pre-graphics delay to pass > igd_init: went through early init > igd_init: RP1 graphics frequency is set > gtt_read(PCH_PORT_HOTPLUG) > --8<-- > > People on IRC mentioned that this is an issue that people may have run > into before on Broadwell, any suggestions on how to fix the hang there? > > > Thanks, > G
Hi Georg, it seems that the refcode binary was not running. Can you verify that it was part of the image and gets executed? Stefan -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
