Hi all,
The attachment was:
Content-Type: text/x-diff;
name="dump.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename="dump.patch"
Lets try again ;)
Thanks
Rudolf
diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig
index c7e7e82..b5a1ba0 100644
--- a/src/mainboard/amd/thatcher/Kconfig
+++ b/src/mainboard/amd/thatcher/Kconfig
@@ -37,7 +37,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
- select SUPERIO_SMSC_LPC47N217
+ select SUPERIO_ITE_IT8712F
select BOARD_ROMSIZE_KB_4096
select TINY_BOOTBLOCK
select GFXUMA
diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h
index 0a1d328..e7880cf 100644
--- a/src/mainboard/amd/thatcher/OptionsIds.h
+++ b/src/mainboard/amd/thatcher/OptionsIds.h
@@ -52,7 +52,7 @@
#define IDSOPT_IDS_ENABLED TRUE
//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 67e4223..f1a4257 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -50,13 +50,13 @@
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT TRUE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
#define INSTALL_FM1_SOCKET_SUPPORT FALSE
-#define INSTALL_FP2_SOCKET_SUPPORT TRUE
+#define INSTALL_FP2_SOCKET_SUPPORT FALSE
#define INSTALL_FT1_SOCKET_SUPPORT FALSE
#define INSTALL_AM3_SOCKET_SUPPORT FALSE
-#define INSTALL_FM2_SOCKET_SUPPORT FALSE
+#define INSTALL_FM2_SOCKET_SUPPORT TRUE
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
@@ -107,7 +107,7 @@
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
@@ -116,12 +116,12 @@
#define BLDCFG_ONLINE_SPARE FALSE
#define BLDCFG_BANK_SWIZZLE TRUE
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
#define BLDCFG_USE_BURST_MODE FALSE
#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE FALSE
#define BLDCFG_ECC_REDIRECTION FALSE
#define BLDCFG_SCRUB_DRAM_RATE 0
#define BLDCFG_SCRUB_L2_RATE 0
@@ -437,13 +437,15 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
// Byte6Seed, Byte7Seed, ByteEccSeed)
// Speicifes the HW RXEN training seed for a channel of a socket
//
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+/*
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
+ */
PSO_END
};
diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb
index 2a91e1a..b03d106 100644
--- a/src/mainboard/amd/thatcher/devicetree.cb
+++ b/src/mainboard/amd/thatcher/devicetree.cb
@@ -30,12 +30,12 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal Multimedia
- device pci 2.0 on end # PCIE SLOT0 x16
- device pci 3.0 on end # PCIE SLOT0 x16
- device pci 4.0 on end # PCIE MINI0
- device pci 5.0 on end # PCIE MINI1
- device pci 6.0 on end # PCIE Slot1 x1
- device pci 7.0 on end # LAN
+ device pci 2.0 off end # PCIE SLOT0 x16
+ device pci 3.0 off end # PCIE SLOT0 x16
+ device pci 4.0 off end # PCIE MINI0
+ device pci 5.0 off end # PCIE MINI1
+ device pci 6.0 off end # PCIE Slot1 x1
+ device pci 7.0 off end # LAN
device pci 8.0 off end # NB/SB Link P2P bridge
end
end
@@ -61,23 +61,47 @@ chip northbridge/amd/agesa/family15tn/root_complex
device i2c 53 on end
end
end # SM
- device pci 14.1 on end # IDE 0x439c
+ device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
- chip superio/smsc/lpc47n217
- device pnp 2e.3 off # Parallel
- io 0x60 = 0x378
- irq 0x70 = 7
+ chip superio/ite/it8712f
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
end
- device pnp 2e.4 on # Com1
+ device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 2e.5 off # Com2
+ device pnp 2e.2 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
- end #superio/smsc/lpc47n217
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 off end # EC
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
+ end
+ device pnp 2e.8 off # MIDI
+ io 0x60 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.9 off # GAME
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8712f
end
device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
device pci 14.5 on end # USB 2
diff --git a/src/mainboard/amd/thatcher/dimmSpd.c b/src/mainboard/amd/thatcher/dimmSpd.c
index 29d6a29..c42439a 100644
--- a/src/mainboard/amd/thatcher/dimmSpd.c
+++ b/src/mainboard/amd/thatcher/dimmSpd.c
@@ -34,8 +34,8 @@ static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm
{
// socket 0
{
- {0xA0, 0x00}, // channel 0 dimms
- {0xA2, 0x00}, // channel 1 dimms
+ {0xA0, 0xA2}, // channel 0 dimms
+ {0xA1, 0xA3}, // channel 1 dimms
},
// socket 1
{
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index e0cfd02..593982c 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -33,7 +33,7 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "southbridge/amd/agesa/hudson/hudson.h"
-#include "src/superio/smsc/lpc47n217/early_serial.c"
+#include "superio/ite/it8712f/early_serial.c"
#include "cpu/amd/agesa/s3_resume.h"
#include "src/drivers/pc80/i8254.c"
#include "src/drivers/pc80/i8259.c"
@@ -44,6 +44,72 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
void disable_cache_as_ram(void);
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO 0xFED80000
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* most likely programming to 48MHz out signal */
+ u32 reg32;
+ reg32 = SB_MMIO_MISC32(0x28);
+ reg32 &= 0xffc7ffff;
+ reg32 |= 0x00100000;
+ SB_MMIO_MISC32(0x28) = reg32;
+
+ reg32 = SB_MMIO_MISC32(0x40);
+ reg32 &= ~0x80u;
+ SB_MMIO_MISC32(0x40) = reg32;
+}
+
+
+
+static void sb800_pci_port80(void)
+{
+ u8 byte;
+ device_t dev;
+
+ /* P2P Bridge */
+ dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
+
+ /* Chip Control: Enable subtractive decoding */
+ byte = pci_read_config8(dev, 0x40);
+ byte |= 1 << 5;
+ pci_write_config8(dev, 0x40, byte);
+
+ /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
+ byte = pci_read_config8(dev, 0x4B);
+ byte |= 1 << 7;
+ pci_write_config8(dev, 0x4B, byte);
+
+ /* The same IO Base and IO Limit here is meaningful because we set the
+ * bridge to be subtractive. During early setup stage, we have to make
+ * sure that data can go through port 0x80.
+ */
+ /* IO Base: 0xf000 */
+ byte = pci_read_config8(dev, 0x1C);
+ byte |= 0xF << 4;
+ pci_write_config8(dev, 0x1C, byte);
+
+ /* IO Limit: 0xf000 */
+ byte = pci_read_config8(dev, 0x1D);
+ byte |= 0xF << 4;
+ pci_write_config8(dev, 0x1D, byte);
+
+ /* PCI Command: Enable IO response */
+ byte = pci_read_config8(dev, 0x04);
+ byte |= 1 << 0;
+ pci_write_config8(dev, 0x04, byte);
+
+ /* LPC controller */
+ dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
+
+ byte = pci_read_config8(dev, 0x4A);
+ byte &= ~(1 << 5); /* disable lpc port 80 */
+ pci_write_config8(dev, 0x4A, byte);
+}
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
@@ -54,24 +120,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
val = agesawrapper_amdinitmmio();
- hudson_lpc_port80();
+// hudson_lpc_port80();
//__asm__ volatile ("1: jmp 1b");
/* TODO: */
+
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+
dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
+// post_code(0x30);
+ sb800_pci_port80();
+ post_code(0x42);
+// it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ /* it8712f_enable_serial does not use its 1st parameter. */
- post_code(0x31);
- lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
+/*
outb(0xea, 0xcd6);
outb(0x1, 0xcd7);
- *(u8 *)0xfed80101 = 0x98;
+*/
+ sbxxx_enable_48mhzout();
+ it8712f_kill_watchdog();
+ it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
console_init();
}
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
