Siyuan Wang ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1497
-gerrit commit f8446823a5cb0716fe64bd8667c8c97179dd8b16 Author: Siyuan Wang <[email protected]> Date: Fri Sep 7 18:35:17 2012 +0800 C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA Currently the C32 has some legacy boards which use the old C32 code. We need to seperate them. CONFIG_CPU_AMD_SOCKET_C32 was used in legacy code before. But it is not a good idea, so we change the code as follows: So we use CONFIG_CPU_AMD_SOCKET_C32 to identify mainboard which uses agesa code, and use CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA to identify mainboard which uses legacy code. Change-Id: If6114bf8912e78b7732f25a1adfb2e4d8eb10ee4 Signed-off-by: Siyuan Wang <[email protected]> Signed-off-by: Siyuan Wang <[email protected]> --- src/cpu/amd/Makefile.inc | 2 +- src/cpu/amd/socket_C32/Kconfig | 14 +++++++------- src/mainboard/supermicro/h8scm_fam10/Kconfig | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index 6663d14..85ce7f6 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -7,7 +7,7 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2 -subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32 +subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32 subdirs-$(CONFIG_CPU_AMD_GEODE_GX1) += geode_gx1 subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2 subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig index 56324dc..db4b624 100644 --- a/src/cpu/amd/socket_C32/Kconfig +++ b/src/cpu/amd/socket_C32/Kconfig @@ -1,4 +1,4 @@ -config CPU_AMD_SOCKET_C32 +config CPU_AMD_SOCKET_C32_NON_AGESA bool select CPU_AMD_MODEL_10XXX select HT3_SUPPORT @@ -8,30 +8,30 @@ config CPU_AMD_SOCKET_C32 config CPU_SOCKET_TYPE hex default 0x14 - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config CBB hex default 0x0 - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config CDB hex default 0x18 - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_SOCKET_C32 + depends on CPU_AMD_SOCKET_C32_NON_AGESA diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index 844763e..44f2d43 100644 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -3,7 +3,7 @@ if BOARD_SUPERMICRO_H8SCM_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_C32 + select CPU_AMD_SOCKET_C32_NON_AGESA select DIMM_DDR3 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
