Kyösti Mälkki ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1431
-gerrit commit 7a9858a9ef017a423ecfca540ba72be69cc54fd2 Author: Kyösti Mälkki <[email protected]> Date: Fri Aug 10 13:28:00 2012 +0300 Redefine IORESOURCE flags for memory Previously IORESOURCE_UMA_FB had a special use as a workaround for AMD TOPMEM setup. With the workaround removed, this can now be treated as a generic flag for uncached MTRR setup as IORESOURCE_MTRR_UC. IORESOURCE_CACHEABLE had two uses: first to identify region as write-back cacheable and second to identify region as usable RAM in coreboot memory table. Split this to IORESOURCE_MTRR_WB and IORESOURCE_FREEMEM, respectively. Rename IORESOURCE_IGNORE_MTRR to IORESOURCE_MTRR_ANY. This should be used with extreme caution. For MMIO resource this is valid only because we know those regions fall outside any write-back region. MMIO resources will change to use IORESOURCE_MTRR_UC once MTRR code can handle/merge them correctly. IORESOURCE_MTRR_xx flags cannot be combined, make it an enumeration with mask IORESOURCE_MTRR_MASK. Change-Id: I6243a662f7ce012842e1d9f908699018d60a3280 Signed-off-by: Kyösti Mälkki <[email protected]> --- src/arch/x86/boot/coreboot_table.c | 2 +- src/cpu/amd/mtrr/amd_mtrr.c | 2 +- src/cpu/x86/mtrr/mtrr.c | 9 ++++----- src/include/device/device.h | 8 ++++---- src/include/device/resource.h | 9 ++++++--- src/northbridge/amd/amdfam10/acpi.c | 2 +- src/northbridge/amd/amdk8/acpi.c | 2 +- 7 files changed, 18 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index d056837..9810db0 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -568,7 +568,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) /* Build the raw table of memory */ search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + IORESOURCE_MEM | IORESOURCE_FREEMEM, IORESOURCE_MEM | IORESOURCE_FREEMEM, build_lb_mem_range, mem); lb_cleanup_memory_ranges(mem); return mem; diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index bff6702..7c7db95 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -190,7 +190,7 @@ void amd_setup_mtrrs(void) state.tomk = state.tom2k = 0; search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + IORESOURCE_MEM | IORESOURCE_MTRR_MASK, IORESOURCE_MEM | IORESOURCE_MTRR_WB, set_fixed_mtrr_resource, &state); printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a061b54..1dba386 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -354,18 +354,17 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) basek = resk(res->base); sizek = resk(res->size); - if (res->flags & IORESOURCE_UMA_FB) { - /* FIXME: could I use Write-Combining for Frame Buffer ? */ + if ((res->flags & IORESOURCE_MTRR_MASK) == IORESOURCE_MTRR_UC) { state->reg = range_to_mtrr(state->reg, basek, sizek, 0, MTRR_TYPE_UNCACHEABLE, state->address_bits, state->above4gb); return; } - if (res->flags & IORESOURCE_IGNORE_MTRR) { + if ((res->flags & IORESOURCE_MTRR_MASK) == IORESOURCE_MTRR_ANY) { return; } - if (!(res->flags & IORESOURCE_CACHEABLE)) + if ((res->flags & IORESOURCE_MTRR_MASK) != IORESOURCE_MTRR_WB) return; /* See if I can merge with the last range @@ -422,7 +421,7 @@ void x86_setup_fixed_mtrrs(void) /* Now see which of the fixed mtrrs cover ram. */ search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + IORESOURCE_MEM | IORESOURCE_MTRR_MASK, IORESOURCE_MEM | IORESOURCE_MTRR_WB, set_fixed_mtrr_resource, NULL); printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); diff --git a/src/include/device/device.h b/src/include/device/device.h index 772b737..c049e12 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -189,16 +189,16 @@ void fixed_mem_resource(device_t dev, unsigned long index, * is used for all UMA except Intel Sandy/IvyBridge. */ #define ram_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_FREEMEM | IORESOURCE_MTRR_WB) #define bad_ram_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_MTRR_ANY) #define uma_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_MTRR_UC) #define mmio_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_MTRR_ANY) void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index ea1bab5..2ad143f 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -13,7 +13,7 @@ #define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ #define IORESOURCE_READONLY 0x00002000 -#define IORESOURCE_CACHEABLE 0x00004000 +#define IORESOURCE_FREEMEM 0x00004000 #define IORESOURCE_RANGELENGTH 0x00008000 #define IORESOURCE_SHADOWABLE 0x00010000 #define IORESOURCE_BUS_HAS_VGA 0x00020000 @@ -21,8 +21,11 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ -#define IORESOURCE_UMA_FB 0x00100000 /* UMA framebuffer */ -#define IORESOURCE_IGNORE_MTRR 0x00200000 /* The resource does not affect MTRR setup. */ + +#define IORESOURCE_MTRR_MASK 0x00f00000 /* MTRR cache types. */ +#define IORESOURCE_MTRR_ANY 0x00000000 /* The resource does not affect MTRR setup. */ +#define IORESOURCE_MTRR_UC 0x00100000 /* The resource creates an explicit un-cached MTRR hole. */ +#define IORESOURCE_MTRR_WB 0x00200000 /* The resource creates or merges with a write-back MTRR region. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 87c2d8c..71ed812 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -121,7 +121,7 @@ unsigned long acpi_fill_srat(unsigned long current) srat_mem_state.current = current; search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + IORESOURCE_MEM | IORESOURCE_FREEMEM, IORESOURCE_MEM | IORESOURCE_FREEMEM, set_srat_mem, &srat_mem_state); current = srat_mem_state.current; diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index ba04da3..9de6624 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -128,7 +128,7 @@ unsigned long acpi_fill_srat(unsigned long current) srat_mem_state.current = current; search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + IORESOURCE_MEM | IORESOURCE_FREEMEM, IORESOURCE_MEM | IORESOURCE_FREEMEM, set_srat_mem, &srat_mem_state); current = srat_mem_state.current; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
