Kyösti Mälkki ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1373
-gerrit commit 37ab40cbfaf4165a7181ed3d1780f6e641f63dd2 Author: Kyösti Mälkki <[email protected]> Date: Fri Jul 27 13:12:03 2012 +0300 Intel Sandybridge and UMA: use mmio_resource() With SandyBridge northbridge code, uma_memory_size was reset to zero before variable MTRRs were set. This mean MTRR setup routine did not previously create a un-cacheable hole. This may not be optimal setup in the number of used MTRRs, but continue with this model until MTRR setup is better. Change-Id: I63c8df19ad6b6350d46a3eca3055abf684b8b114 Signed-off-by: Kyösti Mälkki <[email protected]> --- src/northbridge/intel/sandybridge/northbridge.c | 16 +++++----------- 1 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0df85a7..5a9388e 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -111,17 +111,11 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size; - printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " - "size=0x%llx\n", uma_memory_base, uma_memory_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Clear these values here so they don't get used by MTRR code */ - uma_memory_base = 0; - uma_memory_size = 0; + /* Using uma_resource() here would fail, as base & size cannot + * be used as-is for a single MTRR. Use separate resources after + * MTRR code is fixed to merge them wisely. + */ + mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
