Patrick Georgi ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1370
-gerrit commit c77481762b54b32abab39e3abf4a197aa1661d29 Author: Patrick Georgi <[email protected]> Date: Fri Jul 27 09:51:32 2012 +0200 libpayload: Fix typo Change-Id: I8708703e497053aa1251f06402bd8ea59bd9d24e Signed-off-by: Patrick Georgi <[email protected]> --- payloads/libpayload/drivers/usb/ohci.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 606e467..2cfabb4 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -54,7 +54,7 @@ ohci_reset (hci_t *controller) OHCI_INST(controller)->opreg->HcCommandStatus = HostControllerReset; mdelay(2); /* wait 2ms */ - OCHI_INST(controller)->opreg->HcControl = 0; + OHCI_INST(controller)->opreg->HcControl = 0; mdelay(10); /* wait 10ms */ } @@ -118,7 +118,7 @@ ohci_init (pcidev_t addr) OHCI_INST (controller)->roothub = controller->devices[0]; controller->bus_address = addr; - /* regarding OHCI spec, Appendix A, BAR_OCHI register description, Table A-4 + /* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4 * BASE ADDRESS only [31-12] bits. All other usually 0, but not all */ controller->reg_base = pci_read_config32 (controller->bus_address, 0x10) & 0xfffff000; // OHCI mandates MMIO, so bit 0 is clear OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
