Kyösti Mälkki ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1206
-gerrit commit 5c4301af466e5396341dd7190f6495bc92b012ac Author: Kyösti Mälkki <[email protected]> Date: Wed Jul 11 08:01:35 2012 +0300 Move setup_uma_memory() to Agesa Family15 northbridge Change-Id: I5705623f5067823fae5986b3bcde58504a463508 Signed-off-by: Kyösti Mälkki <[email protected]> --- src/mainboard/amd/dinar/mainboard.c | 44 +------------------- src/northbridge/amd/agesa/family15/northbridge.c | 48 ++++++++++++++++++++++ 2 files changed, 49 insertions(+), 43 deletions(-) diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 8eea6da..0ac6662 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -28,7 +28,6 @@ #include <NbPlatform.h> #include "chip.h" -#define ONE_MB 0x100000 //#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void *nbconfig); @@ -74,48 +73,7 @@ void set_pcie_dereset(void *nbconfig) static void dinar_enable(device_t dev) { printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); -#if CONFIG_GFXUMA - msr_t msr, msr2; - uint32_t sys_mem; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - - /* refer to UMA Size Consideration in Family15h BKDG. */ - /* Please reference MemNGetUmaSizeOR () */ - /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M - */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; - } else { - uma_memory_size = 64 * ONE_MB; - } - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ - - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */ - uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */ -#endif - + setup_uma_memory(); } int add_mainboard_resources(struct lb_memory *mem) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d9da183..c6cbbed 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -31,6 +31,7 @@ #include <cbmem.h> #include <cpu/x86/lapic.h> +#include <cpu/amd/mtrr.h> #include <Porting.h> #include <AGESA.h> @@ -626,6 +627,53 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif +#define ONE_MB 0x100000 + +void setup_uma_memory(void) +{ +#if CONFIG_GFXUMA + msr_t msr, msr2; + uint32_t sys_mem; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in Family15h BKDG. */ + /* Please reference MemNGetUmaSizeOR () */ + /* + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M + */ + sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { + uma_memory_size = 512 * ONE_MB; + } else if (sys_mem >= 1024 * ONE_MB) { + uma_memory_size = 256 * ONE_MB; + } else { + uma_memory_size = 64 * ONE_MB; + } + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */ + uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */ +#endif +} + static void domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
