Jonathan A. Kollasch ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1205
-gerrit commit d43938adbd704c81d438d370fda471578c44e90d Author: Jonathan A. Kollasch <[email protected]> Date: Tue Jul 10 10:14:17 2012 -0500 Lenovo X60: correct SDHCI write protect polarity Change-Id: I916deffe2c692042f7e54c936902e77770ee69df Signed-off-by: Jonathan A. Kollasch <[email protected]> --- src/include/device/pci_ids.h | 1 + src/mainboard/lenovo/x60/mainboard.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ee92594..fd886da 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1525,6 +1525,7 @@ #define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 #define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 #define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 +#define PCI_DEVICE_ID_RICOH_R5C822 0x0822 #define PCI_VENDOR_ID_ARTOP 0x1191 #define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index b45342a..453cf38 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -29,6 +29,7 @@ #include "chip.h" #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/pci_ids.h> #include <arch/io.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> @@ -52,7 +53,7 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_enable(device_t dev) { - device_t dev0, idedev; + device_t dev0, idedev, sdhci_dev; u8 defaults_loaded = 0; ec_clr_bit(0x03, 2); @@ -79,6 +80,19 @@ static void mainboard_enable(device_t dev) ec_write(0x0c, 0x04); } + /* Set SDHCI write protect polarity "SDWPPol" */ + sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0); + if (sdhci_dev) { + if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) { + /* unlock */ + pci_write_config8(sdhci_dev, 0xf9, 0xfc); + /* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */ + pci_write_config8(sdhci_dev, 0xfa, 0x20); + /* restore lock */ + pci_write_config8(sdhci_dev, 0xf9, 0x00); + } + } + if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); defaults_loaded = 0; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
