Author: stuge Date: Sat Jun 4 17:47:30 2011 New Revision: 6634 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6634
Log: Port persimmon r6592 to e350m1: Update GPP port configuration Signed-off-by: Peter Stuge <[email protected]> Acked-by: Marshall Buschman <[email protected]> Modified: trunk/src/mainboard/asrock/e350m1/devicetree.cb Modified: trunk/src/mainboard/asrock/e350m1/devicetree.cb ============================================================================== --- trunk/src/mainboard/asrock/e350m1/devicetree.cb Sat Jun 4 17:47:05 2011 (r6633) +++ trunk/src/mainboard/asrock/e350m1/devicetree.cb Sat Jun 4 17:47:30 2011 (r6634) @@ -99,12 +99,12 @@ end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx_wrapper/sb800 # end # device pci 18.0 # These seem unnecessary -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
