Author: stuge Date: Sat Jun 4 17:45:12 2011 New Revision: 6627 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6627
Log: Port persimmon r6584 and r6601 to e350m1: SPI prefetch early Enable SPI cacheline prefetch early to reduce boot time. Signed-off-by: Marshall Buschman <[email protected]> Acked-by: Peter Stuge <[email protected]> Modified: trunk/src/mainboard/asrock/e350m1/romstage.c Modified: trunk/src/mainboard/asrock/e350m1/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:44:54 2011 (r6626) +++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:45:12 2011 (r6627) @@ -50,6 +50,13 @@ // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); + // early enable of PrefetchEnSPIFromHost + if (boot_cpu()) + { + __outdword (0xcf8, 0x8000a3b8); + __outdword (0xcfc, __indword (0xcfc) | 1 << 24); + } + // early enable of SPI 33 MHz fast mode read if (boot_cpu()) { -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
