Author: myles Date: Fri Apr 30 22:36:02 2010 New Revision: 5519 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5519
Log: Factor out casmap calculation. Gets rid of a warning. Signed-off-by: Myles Watson <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/northbridge/amd/lx/raminit.c Modified: trunk/src/northbridge/amd/lx/raminit.c ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.c Fri Apr 30 22:30:47 2010 (r5518) +++ trunk/src/northbridge/amd/lx/raminit.c Fri Apr 30 22:36:02 2010 (r5519) @@ -238,46 +238,23 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */ -static void setCAS(void) +static u8 getcasmap(u32 dimm, u16 glspeed) { -/*;***************************************************************************** -;* -;* setCAS -;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency -;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 -;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 -;* -;* The CAS setting is based on the information provided in each DIMMs SPD. -;* The speed at which a DIMM can run is described relative to the slowest -;* CAS the DIMM supports. Each speed for the relative CAS settings is -;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink -;* speed, the CAS setting is removed from the list of good settings for -;* the DIMM. This is done for both DIMMs and the lists are compared to -;* find the lowest common CAS latency setting. If there are no CAS settings -;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt. -;* -;* Entry: -;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information. -;* Destroys: We really use everything ! -;*****************************************************************************/ - uint16_t glspeed, dimm_speed; - uint8_t spd_byte, casmap0, casmap1, casmap_shift; - msr_t msr; - - glspeed = GeodeLinkSpeed(); + u16 dimm_speed; + u8 spd_byte, casmap, casmap_shift=0; /************************** DIMM0 **********************************/ - casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES); - if (casmap0 != 0xFF) { + casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); + if (casmap != 0xFF) { /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND); + spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); + spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); @@ -290,52 +267,53 @@ } } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ /* set the casmap based on the shift to limit possible CAS settings */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap0); + spd_byte = 31 - __builtin_clz((uint32_t) casmap); /* just want bits in the lower byte since we have to cast to a 32 */ - casmap0 &= 0xFF << (spd_byte - casmap_shift); + casmap &= 0xFF << (spd_byte - casmap_shift); } else { /* No DIMM */ - casmap0 = 0; + casmap = 0; } + return casmap; +} - /************************** DIMM1 **********************************/ - casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES); - if (casmap1 != 0xFF) { - /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND); - if (spd_byte != 0) { - /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); - if (dimm_speed >= glspeed) { - casmap_shift = 1; /* -.5 is a shift of 1 */ - /* IF -1 timing is supported, check -1 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD); - if (spd_byte != 0) { - /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); - if (dimm_speed >= glspeed) { - casmap_shift = 2; /* -1 is a shift of 2 */ - } - /* note that the -1 result doesn't need to change the available CAS map */ - } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */ - } else { - casmap_shift = 0; - } - } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ - /* set the casmap based on the shift to limit possible CAS settings */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap1); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap1 &= 0xFF << (spd_byte - casmap_shift); - } else { /* No DIMM */ - casmap1 = 0; - } +static void setCAS(void) +{ +/*;***************************************************************************** +;* +;* setCAS +;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency +;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 +;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 +;* +;* The CAS setting is based on the information provided in each DIMMs SPD. +;* The speed at which a DIMM can run is described relative to the slowest +;* CAS the DIMM supports. Each speed for the relative CAS settings is +;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink +;* speed, the CAS setting is removed from the list of good settings for +;* the DIMM. This is done for both DIMMs and the lists are compared to +;* find the lowest common CAS latency setting. If there are no CAS settings +;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt. +;* +;* Entry: +;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information. +;* Destroys: We really use everything ! +;*****************************************************************************/ + uint16_t glspeed; + uint8_t spd_byte, casmap0, casmap1; + msr_t msr; + + glspeed = GeodeLinkSpeed(); + + casmap0 = getcasmap(DIMM0, glspeed); + casmap1 = getcasmap(DIMM1, glspeed); /********************* CAS_LAT MAP COMPARE ***************************/ if (casmap0 == 0) { - spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)]; + spd_byte = CASDDR[__builtin_ctz(casmap1)]; } else if (casmap1 == 0) { - spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; + spd_byte = CASDDR[__builtin_ctz(casmap0)]; } else if ((casmap0 &= casmap1)) { - spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; + spd_byte = CASDDR[__builtin_ctz(casmap0)]; } else { print_emerg("DIMM CAS Latencies not compatible\n"); post_code(ERROR_DIFF_DIMMS); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
