> Found! > > According to some kernel sources and the differences in the pci-registers > between proprietary bios and coreboot there are two values which are > needed: > > AMD_CABLE_DETECT = 0x42 > AMD_UDMA_TIMING = 0x50 > > But, for PCI_VENDOR_ID_NVIDIA an offset of 0x10 has to be added, which > means: AMD_CABLE_DETECT = 0x52 > AMD_UDMA_TIMING = 0x60 > > PCI registers on coreboot address 0x52 (from the IDE device) has value FF > while proprietary has value 99. This is the so called "CABLE_BIT". > > And as the second stuff needed, the AMD_UDMA_TIMING registers is as > follows: The kernel reads the whole address range from 0x60-0x92 and does > some magic stuff to verify if everything is correct. > > On the proprietary bios we have in this range in the pci-registers: > 60: 00 00 c5 c7 00 00 00 00 00 00 00 00 00 00 00 00 > On coreboot we have: > 60: 00 00 c0 c0 00 00 00 00 00 00 00 00 00 00 00 00 > > Thats what to do, but when? - Maybe tomorrow.
Oh, I wanted to attach some files here so it's easy to verify. amd_cable_detect.c is some cp&paste from amd_74xx.c under drivers/ide from the linux sources. > > //Peter > > Regards, > Harald
enum {
AMD_IDE_CONFIG = 0x41,
AMD_CABLE_DETECT = 0x42, //40w=; 80w=; //(AMD_CABLE_DETECT + offset) = 0x52
AMD_DRIVE_TIMING = 0x48,
AMD_8BIT_TIMING = 0x4e,
AMD_ADDRESS_SETUP = 0x4c,
AMD_UDMA_TIMING = 0x50, //33=; 66=; //(AMD_UDMA_TIMING + offset) = 0x60
};
static inline u8 amd_offset(struct pci_dev *dev)
{
return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0; //offset = 0x10
}
static void amd7411_cable_detect(struct pci_dev *dev)
{
int i;
u32 u = 0;
u8 t = 0, offset = amd_offset(dev);
pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
for (i = 24; i >= 0; i -= 8)
if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set "
"cable bits correctly. Enabling workaround.\n",
pci_name(dev));
amd_80w |= (1 << (1 - (i >> 4)));
}
}
00:04.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) 00: de 10 6e 03 05 00 b0 00 a1 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: c1 3c 00 00 00 00 00 00 00 00 00 00 22 10 80 2b 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 40: 22 10 80 2b 01 00 02 00 00 00 00 00 00 00 00 00 50: 02 f0 00 00 00 00 00 00 a8 a8 20 20 0f 00 ff 20 60: 00 00 c0 c0 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 e0 20 f0 00 00 02 30 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 1c 00 00 00 00 00 00 00
00:04.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) 00: de 10 6e 03 05 00 b0 00 a1 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 f0 00 00 00 00 00 00 00 00 00 00 58 14 02 50 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 40: 58 14 02 50 01 00 02 00 00 00 00 00 00 00 00 00 50: 02 f0 00 00 00 00 00 00 a8 a8 20 20 0a 00 99 20 60: 00 00 c5 c7 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 50 ca 23 00 00 02 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00
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