Hey Jon,
Harrison, Jon (SELEX GALILEO, UK) wrote:
> Attached is v5 of the CN400/EPIA-NL patch for Coreboot V2.
>
> This has been built and tested against R4404.
>
> The status as follows:
> 1/ Board sucessfully boots and launches FILO 0.6.0 payload.
> 2/ VGA framebuffer seems to work OK. (with factory VGA BIOS and BOCHS
> helpers)
Nice progress! Other than my few concerns, I think this is a good
patch.
Content-Description: cn400-patch-v5.patch
> Index: src/mainboard/via/epia-n/Config.lb
..
> -chip northbridge/via/cn400 # Northbridge
..
> +chip northbridge/via/cn400 # Northbridge
It seems that there are quite a few whitespace only changes in this
patch. It would be very helpful if you could split up the patch into
several parts; one for functional changes and one for whitespace
corrections.
> Index: src/northbridge/via/cn400/northbridge.c
..
> @@ -193,27 +202,29 @@
>
> /*
> * Once the register value is not zero, the RAM size is
> - * this register's value multiply 64 * 1024 * 1024.
> - */
> + * this register's value multiply 32 * 1024 * 1024.
> + *
> for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
> rambits = pci_read_config8(mc_dev, ramregs[i]);
> if (rambits != 0)
> break;
> }
> -
> - tomk = rambits * 64 * 1024;
> - printk_spew("tomk is 0x%x\n", tomk);
> + */
> + rambits = pci_read_config8(mc_dev, 0x47);
> + tomk = rambits * 32 * 1024;
This hunk is really too tricky. Please remove the lines if they
should not be in there.
Thanks!
//Peter
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