Hrm. This is the AR register accesses. They require a read from STAT1 for the internal counter to be reset and thus for correct read/write operations.
I inserted a delay there, now it works. The bios has there just some CALL and I have it in one instruction stream. Maybe it is too fast.
Rudolf -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
