On 12.08.2008 21:53, Mart Raudsepp wrote: > artecgroup/dbe62: Fix SPD_NUM_COLUMNS value (DIMM page size) > > This changes SPD_NUM_COLUMNS from 0x8 back to 0xa, as it was originally when > copied over from another board, because 0x8 evaluates to 2kB, not 8kB, while > 0xa > does the latter. 8kB is what the chip has and what is also set in our > currently > used firmwares for DBE62. > > This (combined with all the previous committed hard work from Ron before) > fixes > memtest86+ freezes and hard reboots for me in quick 30 minute testing time, > while before it would freeze or reboot just into 50% of first test. > > There is more to do to get the optimum RAM setup, but this should do for now - > the rest is just optimizing to quicker timings, while current ones in the fake > SPD are very conservative. > > Signed-off-by: Mart Raudsepp <[EMAIL PROTECTED]> >
Cool! Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
