On 22.01.2008 12:08, Harald Gutmann wrote: > Am Dienstag, 22. Januar 2008 01:09:09 schrieben Sie: > >> Harald: This patch should fix your problems writing to the chip. Use >> either "patch -l" or remove the // before >> //while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) >> > I've updated my flashrom tree to revision 3068 and commented that line out. > Now i can flash the chip, like Ronald says. I wrote the chip, and read the > file again, and compared the start and the end of the file with > hexdump/head/tail and diff. On the first/last 50000 lines there is no > difference between the file which was written to the chip, and the file i've > read with flashrom from the chip. > > Any idea why verifying fails? >
Yes. Will send a patch. >> Ronald: I need an ack to commit this. >> >> On 20.01.2008 11:59, Ronald Hoogenboom wrote: >> >>> Carl-Daniel Hailfinger wrote: >>> >>>> Did you have time to test with the while >>>> (generic_spi_read_status_register() & .._WIP) enabled? It would be more >>>> correct to have it enabled. >>>> >>> I had that in initially (that's why it was there, but commented out) but >>> all it got me was slower programming times and the datasheet also >>> suggests it is ok to just do a timed wait. But in the face of >>> genericness for other chips, it is indeed more correct to do the check >>> for the busy bit. >>> >> Ronald/Harald, can you please ack the change? It is reproduced below >> (whichspace-damaged). >> >> Regards, >> Carl-Daniel >> >> Make sure we delay writing the next byte long enough in SPI byte >> programming. >> Minor formatting changes. >> >> Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> >> > Acked-by: Harald Gutmann <[EMAIL PROTECTED]> > Thanks, r3069. Regards, Carl-Daniel -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
