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from d7282a32c2 [BugFix][LLVM] Fix `insertDeclare` API mismatch for
ROCm-bundled LLVM 20 (#19390)
add a8f1aced2f [FIX] Skip metal target tag registration for unsupported
LLVM CPUs (#19427)
No new revisions were added by this update.
Summary of changes:
python/tvm/target/codegen.py | 18 ++++++++++++++++++
python/tvm/target/tag_registry/metal.py | 11 ++++++++++-
src/target/llvm/llvm_module.cc | 9 +++++++++
3 files changed, 37 insertions(+), 1 deletion(-)
