lipan118 commented on PR #9977:
URL: https://github.com/apache/nuttx/pull/9977#issuecomment-1661397472
> @lipan118 thank you for your explanation, it now makes sense.
>
> However, maybe we should also check that ` RCC_BDCR_LSERDY` is set? What
if the RTC is initialized, but for some reason (e.g. h/w fault), the clock
stops? It will be impossible to be restart.
This process is implemented by default in the function void
stm32_rcc_enablelse(void).
```
void stm32_rcc_enablelse(void)
{
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
stm32_pwr_enablebkp(true);
#if defined(CONFIG_STM32_STM32L15XX)
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
* the RCC CSR register.
*/
modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSEON);
/* Wait for the LSE clock to be ready */
while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSERDY) == 0)
{
stm32_waste();
}
#else
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
* the RCC BDCR register.
*/
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
/* Wait for the LSE clock to be ready */
while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
{
stm32_waste();
}
#endif
/* Disable backup domain access if it was disabled on entry */
stm32_pwr_enablebkp(false);
}
```
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