no1wudi opened a new pull request, #8928: URL: https://github.com/apache/nuttx/pull/8928
## Summary RISCV has a modular instruction set. It's hard to define cpu-model to support all toolchain. For Zig, cpu model is this formal: generic_rv[32|64][i][m][a][f][d][c] For Rust, cpu model is this formal: riscv[32|64][i][m][a][f][d][c] So, it's better to map the NuttX config to LLVM builtin cpu model, these models supported by all LLVM based toolchain. Refer to : https://github.com/llvm/llvm-project/blob/release/15.x/llvm/lib/Target/RISCV/RISCV.td These models can't cover all implementation of RISCV, but it's enough for most cases (All NuttX supported chips). ## Impact non-c compiler only ## Testing CI and local machine -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
