This is an automated email from the ASF dual-hosted git repository.
gustavonihei pushed a commit to branch feature/sync_hal_5
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit c25cec7d44cd5e23f23374f46d0f0649a49722fc
Author: Gustavo Henrique Nihei <gustavo.ni...@espressif.com>
AuthorDate: Fri Feb 10 19:17:37 2023 -0300
risc-v/espressif: Add support for ESP32-C6
Signed-off-by: Gustavo Henrique Nihei <gustavo.ni...@espressif.com>
---
arch/risc-v/src/espressif/Kconfig | 59 ++-
arch/risc-v/src/espressif/Make.defs | 2 +-
arch/risc-v/src/espressif/esp_irq.c | 441 ++++++++++-----------
arch/risc-v/src/espressif/esp_irq.h | 31 +-
arch/risc-v/src/espressif/esp_lowputc.c | 4 +-
arch/risc-v/src/espressif/esp_lowputc.h | 2 +-
arch/risc-v/src/espressif/esp_serial.c | 113 ++----
arch/risc-v/src/espressif/esp_timerisr.c | 17 +-
arch/risc-v/src/espressif/hal_esp32c6.mk | 96 +++++
boards/Kconfig | 10 +
.../common/scripts/esp32c3_legacy_sections.ld | 47 ++-
.../espressif/common/scripts/esp32c6_aliases.ld | 29 ++
.../common/scripts/esp32c6_flat_memory.ld | 109 +++++
...gacy_sections.ld => esp32c6_legacy_sections.ld} | 120 +++---
boards/risc-v/espressif/esp32c6-generic/Kconfig | 8 +
.../esp32c6-generic/configs/nsh/defconfig | 57 +++
.../espressif/esp32c6-generic/include/board.h | 25 ++
.../espressif/esp32c6-generic/scripts/Make.defs | 60 +++
.../risc-v/espressif/esp32c6-generic/src/Make.defs | 31 ++
.../esp32c6-generic/src/esp32c6-generic.h | 72 ++++
.../esp32c6-generic/src/esp32c6_appinit.c | 81 ++++
.../espressif/esp32c6-generic/src/esp32c6_boot.c | 89 +++++
.../esp32c6-generic/src/esp32c6_bringup.c | 100 +++++
tools/espressif/Config.mk | 24 +-
24 files changed, 1204 insertions(+), 423 deletions(-)
diff --git a/arch/risc-v/src/espressif/Kconfig
b/arch/risc-v/src/espressif/Kconfig
index 3842d89bd4..3fedef6c70 100644
--- a/arch/risc-v/src/espressif/Kconfig
+++ b/arch/risc-v/src/espressif/Kconfig
@@ -35,16 +35,41 @@ config ESPRESSIF_ESP32C3
---help---
ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash
memory
+config ESPRESSIF_ESP32C6
+ bool "ESP32-C6"
+ select ARCH_RV32
+ select ARCH_RV_ISA_M
+ select ARCH_RV_ISA_A
+ select ARCH_RV_ISA_C
+ select ARCH_VECNOTIRQ
+ select ARCH_HAVE_MPU
+ select ARCH_HAVE_RESET
+ select LIBC_ARCH_MEMCPY
+ select LIBC_ARCH_MEMCHR
+ select LIBC_ARCH_MEMCMP
+ select LIBC_ARCH_MEMMOVE
+ select LIBC_ARCH_MEMSET
+ select LIBC_ARCH_STRCHR
+ select LIBC_ARCH_STRCMP
+ select LIBC_ARCH_STRCPY
+ select LIBC_ARCH_STRLCPY
+ select LIBC_ARCH_STRNCPY
+ select LIBC_ARCH_STRLEN
+ select LIBC_ARCH_STRNLEN
+ ---help---
+ Espressif ESP32-C6 (RV32IMAC).
+
endchoice # ESPRESSIF_CHIP_SERIES
config ESPRESSIF_CHIP_SERIES
string
default "esp32c3" if ESPRESSIF_ESP32C3
+ default "esp32c6" if ESPRESSIF_ESP32C6
default "unknown"
choice ESPRESSIF_FLASH
prompt "Flash Size"
- default ESPRESSIF_FLASH_4M if ESPRESSIF_ESP32C3
+ default ESPRESSIF_FLASH_4M if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6
config ESPRESSIF_FLASH_2M
bool "2 MB"
@@ -62,7 +87,7 @@ config ESPRESSIF_FLASH_DETECT
choice ESPRESSIF_CPU_FREQ
prompt "CPU frequency"
- default ESPRESSIF_CPU_FREQ_160 if ESPRESSIF_ESP32C3
+ default ESPRESSIF_CPU_FREQ_160 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6
---help---
CPU frequency to be set on application startup.
@@ -141,22 +166,32 @@ if ESPRESSIF_UART0
config ESPRESSIF_UART0_TXPIN
int "UART0 TX Pin"
default 21 if ESPRESSIF_ESP32C3
+ default 16 if ESPRESSIF_ESP32C6
+ range 0 21 if ESPRESSIF_ESP32C3
+ range 0 30 if ESPRESSIF_ESP32C6
config ESPRESSIF_UART0_RXPIN
int "UART0 RX Pin"
default 20 if ESPRESSIF_ESP32C3
+ default 17 if ESPRESSIF_ESP32C6
+ range 0 21 if ESPRESSIF_ESP32C3
+ range 0 30 if ESPRESSIF_ESP32C6
config ESPRESSIF_UART0_RTSPIN
int "UART0 RTS Pin"
depends on SERIAL_IFLOWCONTROL
default 16 if ESPRESSIF_ESP32C3
- range 0 21
+ default 15 if ESPRESSIF_ESP32C6
+ range 0 21 if ESPRESSIF_ESP32C3
+ range 0 30 if ESPRESSIF_ESP32C6
config ESPRESSIF_UART0_CTSPIN
int "UART0 CTS Pin"
depends on SERIAL_OFLOWCONTROL
default 15 if ESPRESSIF_ESP32C3
- range 0 21
+ default 14 if ESPRESSIF_ESP32C6
+ range 0 21 if ESPRESSIF_ESP32C3
+ range 0 30 if ESPRESSIF_ESP32C6
endif # ESPRESSIF_UART0
@@ -164,23 +199,25 @@ if ESPRESSIF_UART1
config ESPRESSIF_UART1_TXPIN
int "UART1 TX Pin"
- default 8 if ESPRESSIF_ESP32C3
+ default 8 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6
config ESPRESSIF_UART1_RXPIN
int "UART1 RX Pin"
- default 9 if ESPRESSIF_ESP32C3
+ default 9 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6
config ESPRESSIF_UART1_RTSPIN
int "UART1 RTS Pin"
depends on SERIAL_IFLOWCONTROL
- default 1 if ESPRESSIF_ESP32C3
- range 0 21
+ default 1 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6
+ range 0 21 if ESPRESSIF_ESP32C3
+ range 0 30 if ESPRESSIF_ESP32C6
config ESPRESSIF_UART1_CTSPIN
int "UART1 CTS Pin"
depends on SERIAL_OFLOWCONTROL
- default 2 if ESPRESSIF_ESP32C3
- range 0 21
+ default 2 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6
+ range 0 21 if ESPRESSIF_ESP32C3
+ range 0 30 if ESPRESSIF_ESP32C6
endif # ESPRESSIF_UART1
@@ -211,7 +248,7 @@ endchoice # ESPRESSIF_FLASH_MODE
choice ESPRESSIF_FLASH_FREQ
prompt "SPI Flash frequency"
- default ESPRESSIF_FLASH_FREQ_40M
+ default ESPRESSIF_FLASH_FREQ_80M if ESPRESSIF_ESP32C3 ||
ESPRESSIF_ESP32C6
---help---
SPI Flash frequency.
diff --git a/arch/risc-v/src/espressif/Make.defs
b/arch/risc-v/src/espressif/Make.defs
index 4f1b589043..050de0acc2 100644
--- a/arch/risc-v/src/espressif/Make.defs
+++ b/arch/risc-v/src/espressif/Make.defs
@@ -41,7 +41,7 @@ CHIP_CSRCS += esp_timerisr.c esp_wdt.c
# Fetch Espressif HAL source files and add them to build
HAL_ESPRESSIF_UNPACK = esp-hal-component
-HAL_ESPRESSIF_ID = c5160ae3
+HAL_ESPRESSIF_ID = 157dbe84
HAL_ESPRESSIF_ZIP = $(HAL_ESPRESSIF_ID).zip
HAL_ESPRESSIF_URL =
https://github.com/gustavonihei/esp-hal-component/archive
diff --git a/arch/risc-v/src/espressif/esp_irq.c
b/arch/risc-v/src/espressif/esp_irq.c
index 9f6fb10f5e..c3a856bd06 100644
--- a/arch/risc-v/src/espressif/esp_irq.c
+++ b/arch/risc-v/src/espressif/esp_irq.c
@@ -38,70 +38,90 @@
#include "esp_irq.h"
#include "esp_attr.h"
-#include "soc/interrupt_reg.h"
+#include "esp_cpu.h"
+#include "esp_rom_sys.h"
+#include "riscv/interrupt.h"
+#include "soc/soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-#define ESP_DEFAULT_INT_THRESHOLD 1
+#define ESP_DEFAULT_INT_THRESHOLD 1
-#define IRQ_UNMAPPED 0xff
+#define IRQ_UNMAPPED 0xff
-/* CPU interrupts to peripheral mapping:
- *
- * Encoding: EPPPPPPP
- * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
- * P: Attached peripheral.
- */
+/* Helper macros for working with cpuint_mapentry_t fields */
-#define CPUINT_UNASSIGNED 0x7f
-#define CPUINT_GETEN(m) (((m) & 0x80) >> 7)
-#define CPUINT_GETIRQ(m) ((m) & 0x7f)
-#define CPUINT_DISABLE(m) ((m) &= 0x7f)
-#define CPUINT_ENABLE(m) ((m) |= 0x80)
-#define CPUINT_ASSIGN(m,c) ((m) = ((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(cpuint) do { (cpuint).cpuint_en = 0; } while(0)
+#define CPUINT_ENABLE(cpuint) do { (cpuint).cpuint_en = 1; } while(0)
+#define CPUINT_ASSIGN(cpuint,i) do \
+ { \
+ (cpuint).assigned = 1; \
+ (cpuint).cpuint_en = 1; \
+ (cpuint).irq = (i); \
+ } \
+ while(0)
+#define CPUINT_FREE(cpuint) do { (cpuint).val = 0; } while(0)
+#define CPUINT_ISENABLED(cpuint) ((cpuint).cpuint_en == 1)
+#define CPUINT_ISASSIGNED(cpuint) ((cpuint).assigned == 1)
+#define CPUINT_ISFREE(cpuint) (!CPUINT_ISASSIGNED(cpuint))
-/* Mapping Peripheral IDs to register addresses */
+/* CPU interrupts can be detached from any interrupt source by setting the
+ * map register to ETS_INVALID_INUM, which is an invalid CPU interrupt index.
+ */
-#define CORE0_PERIPH_REG(periphid) \
- (DR_REG_INTERRUPT_CORE0_BASE + ((periphid) << 2))
+#define NO_CPUINT ETS_INVALID_INUM
-/* Mapping CPU Interrupt IDs to priority register addresses */
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
-#define CORE0_PRIO_REG(cpuint) \
- (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + ((cpuint) << 2))
+/* CPU interrupts to IRQ index mapping */
-/* CPU interrupts can be detached from any peripheral source by setting the
- * map register to 0, which is an invalid CPU interrupt index.
- */
+typedef union cpuint_mapentry_u
+{
+ struct
+ {
+ uint16_t assigned:1;
+ uint16_t cpuint_en:1;
+ uint16_t irq:10;
+ uint16_t reserved0:4;
+ };
-#define NO_CPUINT 0
+ uint16_t val;
+} cpuint_mapentry_t;
/****************************************************************************
* Private Data
****************************************************************************/
-/* Map a CPU interrupt to the IRQ of the attached peripheral interrupt */
+/* Map a CPU interrupt to the IRQ of the attached interrupt source */
-static uint8_t g_cpu_intmap[ESP_NCPUINTS];
+static cpuint_mapentry_t g_cpuint_map[ESP_NCPUINTS];
-/* Map an IRQ to a CPU interrupt to which the peripheral interrupt is
+/* Map an IRQ to a CPU interrupt to which the interrupt source is
* attached to.
*/
-static volatile uint8_t g_irqmap[NR_IRQS];
+static volatile uint8_t g_irq_map[NR_IRQS];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpuint_freelist = ESP_CPUINT_PERIPHSET;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
- * Name: esp_getcpuint
+ * Name: esp_cpuint_alloc
*
* Description:
- * Get a free CPU interrupt for a peripheral device. This function will
- * not ignore all of the pre-allocated CPU interrupts for internal
+ * Allocate a free CPU interrupt for a peripheral device. This function
+ * will not ignore all of the pre-allocated CPU interrupts for internal
* devices.
*
* Input Parameters:
@@ -113,260 +133,228 @@ static volatile uint8_t g_irqmap[NR_IRQS];
*
****************************************************************************/
-static int esp_getcpuint(void)
+static int esp_cpuint_alloc(void)
{
+ uint32_t bitmask;
+ uint32_t intset;
int cpuint;
+ int ret = -ENOMEM;
/* Check if there are CPU interrupts with the requested properties
* available.
*/
- for (cpuint = ESP_CPUINT_MIN; cpuint <= ESP_CPUINT_MAX; cpuint++)
+ intset = g_cpuint_freelist;
+ if (intset != 0)
{
- if (g_cpu_intmap[cpuint] == CPUINT_UNASSIGNED)
+ /* Skip over initial unavailable CPU interrupts quickly in groups
+ * of 8 interrupt.
+ */
+
+ for (cpuint = 0, bitmask = 0xff;
+ cpuint < ESP_NCPUINTS && (intset & bitmask) == 0;
+ cpuint += 8, bitmask <<= 8);
+
+ /* Search for an unallocated CPU interrupt number in the remaining
+ * intset.
+ */
+
+ for (; cpuint < ESP_NCPUINTS; cpuint++)
{
- break;
+ /* If the bit corresponding to the CPU interrupt is '1', then
+ * that CPU interrupt is available.
+ */
+
+ bitmask = UINT32_C(1) << cpuint;
+ if ((intset & bitmask) != 0)
+ {
+ /* Got it! */
+
+ g_cpuint_freelist &= ~bitmask;
+ ret = cpuint;
+ break;
+ }
}
}
- if (cpuint > ESP_CPUINT_MAX)
- {
- return -ENOMEM;
- }
-
/* Enable the CPU interrupt now. The interrupt is still not attached
- * to any peripheral and thus has no effect.
+ * to any interrupt source and thus has no effect.
*/
- modifyreg32(INTERRUPT_CORE0_CPU_INT_ENABLE_REG, 0, UINT32_C(1) << cpuint);
+ if (ret >= 0)
+ {
+ esprv_intc_int_enable(UINT32_C(1) << ret);
+ }
- return cpuint;
+ return ret;
}
/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_irqinitialize
+ * Name: esp_cpuint_free
*
* Description:
- * Complete initialization of the interrupt system and enable normal,
- * interrupt processing.
+ * Free a previously allocated CPU interrupt.
*
* Input Parameters:
- * None.
+ * cpuint - The CPU interrupt number to be freed.
*
* Returned Value:
* None.
*
****************************************************************************/
-void up_irqinitialize(void)
+static void esp_cpuint_free(int cpuint)
{
- /* Indicate that no peripheral interrupts are assigned to CPU interrupts */
-
- for (int i = 0; i < NR_IRQS; i++)
- {
- g_irqmap[i] = IRQ_UNMAPPED;
- }
-
- /* Initialize CPU interrupts */
+ uint32_t bitmask;
- esp_cpuint_initialize();
+ DEBUGASSERT(cpuint >= 0 && cpuint < ESP_NCPUINTS);
+ DEBUGASSERT(CPUINT_ISASSIGNED(g_cpuint_map[cpuint]));
- /* Initialize specific CPU interrupts of some drivers:
- * Object | CPU INT | Peripheral
- * | |
- * Wi-Fi | 1 | 1
- * BT BB | 5 | 5
- * RW BLE | 8 | 8
- */
-
-#ifdef CONFIG_ESPRESSIF_WIFI
- g_irqmap[ESP_IRQ_MAC_NMI] = ESP_CPUINT_MAC_NMI;
- g_cpu_intmap[ESP_CPUINT_MAC_NMI] = CPUINT_ASSIGN(ESP_IRQ_MAC_NMI);
-#endif
-
-#ifdef CONFIG_ESPRESSIF_BLE
- g_irqmap[ESP_IRQ_BT_BB] = ESP_CPUINT_BT_BB;
- g_irqmap[ESP_IRQ_RWBLE] = ESP_CPUINT_RWBLE;
- g_cpu_intmap[ESP_CPUINT_BT_BB] = CPUINT_ASSIGN(ESP_IRQ_BT_BB);
- g_cpu_intmap[ESP_CPUINT_RWBLE] = CPUINT_ASSIGN(ESP_IRQ_RWBLE);
-#endif
-
- /* Attach the common interrupt handler */
+ CPUINT_FREE(g_cpuint_map[cpuint]);
- riscv_exception_attach();
+ /* Mark the CPU interrupt as available */
-#ifndef CONFIG_SUPPRESS_INTERRUPTS
+ bitmask = UINT32_C(1) << cpuint;
- /* And finally, enable interrupts */
+ DEBUGASSERT((g_cpuint_freelist & bitmask) == 0);
- up_irq_enable();
-#endif
+ g_cpuint_freelist |= bitmask;
}
/****************************************************************************
- * Name: up_enable_irq
+ * Name: esp_cpuint_initialize
*
* Description:
- * Enable the interrupt specified by 'irq'.
+ * Initialize CPU interrupts.
*
* Input Parameters:
- * irq - IRQ number.
+ * None.
*
* Returned Value:
* None.
*
****************************************************************************/
-void up_enable_irq(int irq)
+static void esp_cpuint_initialize(void)
{
- int cpuint = g_irqmap[irq];
- irqstate_t irqstate;
+ /* Unmap CPU interrupts from every interrupt source */
- irqinfo("irq=%d | cpuint=%d \n", irq, cpuint);
+ for (int source = 0; source < ESP_NSOURCES; source++)
+ {
+ esp_rom_route_intr_matrix(PRO_CPU_NUM, source, NO_CPUINT);
+ }
- DEBUGASSERT(cpuint >= ESP_CPUINT_MIN && cpuint <= ESP_CPUINT_MAX);
+ /* Set CPU interrupt threshold level */
- CPUINT_ENABLE(g_cpu_intmap[cpuint]);
+ esprv_intc_int_set_threshold(ESP_DEFAULT_INT_THRESHOLD);
- irqstate = enter_critical_section();
- modifyreg32(INTERRUPT_CORE0_CPU_INT_ENABLE_REG, 0, UINT32_C(1) << cpuint);
- leave_critical_section(irqstate);
+ /* Indicate that no interrupt sources are assigned to CPU interrupts */
+
+ memset(g_cpuint_map, 0, sizeof(g_cpuint_map));
}
/****************************************************************************
- * Name: up_disable_irq
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
*
* Description:
- * Disable the interrupt specified by 'irq'.
+ * Complete initialization of the interrupt system and enable normal,
+ * interrupt processing.
*
* Input Parameters:
- * irq - IRQ number.
+ * None.
*
* Returned Value:
* None.
*
****************************************************************************/
-void up_disable_irq(int irq)
+void up_irqinitialize(void)
{
- int cpuint = g_irqmap[irq];
+ /* Indicate that no interrupt sources are assigned to CPU interrupts */
- irqinfo("irq=%d | cpuint=%d \n", irq, cpuint);
+ for (int i = 0; i < NR_IRQS; i++)
+ {
+ g_irq_map[i] = IRQ_UNMAPPED;
+ }
- DEBUGASSERT(cpuint >= ESP_CPUINT_MIN && cpuint <= ESP_CPUINT_MAX);
+ /* Initialize CPU interrupts */
- if (cpuint == IRQ_UNMAPPED)
- {
- /* This interrupt is already disabled. */
+ esp_cpuint_initialize();
- return;
- }
- else
- {
- irqstate_t irqstate;
+ /* Attach the common interrupt handler */
+
+ riscv_exception_attach();
- CPUINT_DISABLE(g_cpu_intmap[cpuint]);
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
- irqstate = enter_critical_section();
- modifyreg32(INTERRUPT_CORE0_CPU_INT_ENABLE_REG, UINT32_C(1) << cpuint,
- 0);
- leave_critical_section(irqstate);
- }
+ /* And finally, enable interrupts */
+
+ up_irq_enable();
+#endif
}
/****************************************************************************
- * Name: esp_free_cpuint
+ * Name: up_enable_irq
*
* Description:
- * Free a previously allocated CPU interrupt.
+ * Enable the interrupt specified by 'irq'.
*
* Input Parameters:
- * cpuint - The CPU interrupt number to be freed.
+ * irq - IRQ number.
*
* Returned Value:
* None.
*
****************************************************************************/
-static void esp_free_cpuint(int cpuint)
+void up_enable_irq(int irq)
{
- irqstate_t irqstate;
- uint8_t periphid;
- int irq;
-
- DEBUGASSERT(cpuint >= ESP_CPUINT_MIN && cpuint <= ESP_CPUINT_MAX);
- DEBUGASSERT(g_cpu_intmap[cpuint] != CPUINT_UNASSIGNED);
-
- irq = CPUINT_GETIRQ(g_cpu_intmap[cpuint]);
- periphid = ESP_IRQ2PERIPH(irq);
+ int cpuint = g_irq_map[irq];
- irqinfo("INFO: irq[%" PRIu8 "]=%" PRIu8 "\n", irq, cpuint);
+ irqinfo("irq=%d | cpuint=%d \n", irq, cpuint);
- /* Undo the allocation process:
- * 1. Unmap the peripheral from the CPU interrupt ID.
- * 2. Reset the interrupt type.
- * 3. Reset the interrupt priority.
- * 4. Clear the CPU interrupt.
- */
+ DEBUGASSERT(cpuint >= 0 && cpuint < ESP_NCPUINTS);
- irqstate = enter_critical_section();
+ irqstate_t irqstate = enter_critical_section();
- g_cpu_intmap[cpuint] = CPUINT_UNASSIGNED;
-
- putreg32(0, CORE0_PERIPH_REG(periphid));
- modifyreg32(INTERRUPT_CORE0_CPU_INT_TYPE_REG,
- UINT32_C(1) << cpuint, 0);
- putreg32(0, CORE0_PRIO_REG(cpuint));
- modifyreg32(INTERRUPT_CORE0_CPU_INT_ENABLE_REG, UINT32_C(1) << cpuint,
- 0);
+ CPUINT_ENABLE(g_cpuint_map[cpuint]);
+ esprv_intc_int_enable(UINT32_C(1) << cpuint);
leave_critical_section(irqstate);
}
/****************************************************************************
- * Name: esp_cpuint_initialize
+ * Name: up_disable_irq
*
* Description:
- * Initialize CPU interrupts.
+ * Disable the interrupt specified by 'irq'.
*
* Input Parameters:
- * None.
+ * irq - IRQ number.
*
* Returned Value:
- * Zero (OK) is returned on success; A negated errno value is returned on
- * any failure.
+ * None.
*
****************************************************************************/
-int esp_cpuint_initialize(void)
+void up_disable_irq(int irq)
{
- /* Disable all CPU interrupts on this CPU */
-
- for (int cpuint = 0; cpuint < ESP_NCPUINTS; cpuint++)
- {
- putreg32(0, CORE0_PRIO_REG(cpuint));
- }
-
- /* Detach all interrupts from peripheral sources */
-
- for (int periphid = 0; periphid < ESP_NPERIPHERALS; periphid++)
- {
- putreg32(0, CORE0_PERIPH_REG(periphid));
- }
+ int cpuint = g_irq_map[irq];
- /* Set CPU interrupt threshold level */
+ irqinfo("irq=%d | cpuint=%d \n", irq, cpuint);
- putreg32(ESP_DEFAULT_INT_THRESHOLD, INTERRUPT_CORE0_CPU_INT_THRESH_REG);
+ DEBUGASSERT(cpuint >= 0 && cpuint < ESP_NCPUINTS);
- /* Indicate that no peripheral interrupts are assigned to CPU interrupts */
+ irqstate_t irqstate = enter_critical_section();
- memset(g_cpu_intmap, CPUINT_UNASSIGNED, ESP_NCPUINTS);
+ CPUINT_DISABLE(g_cpuint_map[cpuint]);
+ esprv_intc_int_disable(UINT32_C(1) << cpuint);
- return OK;
+ leave_critical_section(irqstate);
}
/****************************************************************************
@@ -377,7 +365,7 @@ int esp_cpuint_initialize(void)
*
* Input Parameters:
* cpuint - CPU interrupt ID.
- * periphid - Peripheral ID.
+ * source - Interrupt source.
* priority - Interrupt priority.
* type - Interrupt trigger type.
*
@@ -386,33 +374,31 @@ int esp_cpuint_initialize(void)
*
****************************************************************************/
-void esp_bind_irq(int cpuint, int periphid, irq_priority_t priority,
+void esp_bind_irq(int cpuint, int source, irq_priority_t priority,
irq_trigger_t type)
{
/* Disable the CPU interrupt. */
- modifyreg32(INTERRUPT_CORE0_CPU_INT_ENABLE_REG, UINT32_C(1) << cpuint, 0);
+ esprv_intc_int_disable(UINT32_C(1) << cpuint);
/* Set the interrupt priority. */
- putreg32(priority, CORE0_PRIO_REG(cpuint));
+ esprv_intc_int_set_priority(cpuint, priority);
/* Set the interrupt trigger type (Edge or Level). */
if (type == ESP_IRQ_TRIGGER_EDGE)
{
- modifyreg32(INTERRUPT_CORE0_CPU_INT_TYPE_REG, 0,
- UINT32_C(1) << cpuint);
+ esprv_intc_int_set_type(cpuint, INTR_TYPE_EDGE);
}
else
{
- modifyreg32(INTERRUPT_CORE0_CPU_INT_TYPE_REG, UINT32_C(1) << cpuint,
- 0);
+ esprv_intc_int_set_type(cpuint, INTR_TYPE_LEVEL);
}
/* Map the CPU interrupt ID to the peripheral. */
- putreg32(cpuint, CORE0_PERIPH_REG(periphid));
+ esp_rom_route_intr_matrix(PRO_CPU_NUM, source, cpuint);
}
/****************************************************************************
@@ -423,7 +409,7 @@ void esp_bind_irq(int cpuint, int periphid, irq_priority_t
priority,
* priority and type and attaches it to the given peripheral.
*
* Input Parameters:
- * periphid - The peripheral number from irq.h to be assigned to
+ * source - The interrupt source from irq.h to be assigned to
* a CPU interrupt.
* priority - Interrupt priority.
* type - Interrupt trigger type.
@@ -434,23 +420,23 @@ void esp_bind_irq(int cpuint, int periphid,
irq_priority_t priority,
*
****************************************************************************/
-int esp_setup_irq(int periphid, irq_priority_t priority, irq_trigger_t type)
+int esp_setup_irq(int source, irq_priority_t priority, irq_trigger_t type)
{
irqstate_t irqstate;
int irq;
int cpuint;
- irqinfo("periphid = %d\n", periphid);
+ irqinfo("source = %d\n", source);
irqstate = enter_critical_section();
/* Setting up an IRQ includes the following steps:
* 1. Allocate a CPU interrupt.
- * 2. Attach that CPU interrupt to the peripheral.
+ * 2. Attach that CPU interrupt to the interrupt source.
* 3. Map the CPU interrupt to the IRQ to ease searching later.
*/
- cpuint = esp_getcpuint();
+ cpuint = esp_cpuint_alloc();
if (cpuint < 0)
{
irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d",
@@ -460,16 +446,16 @@ int esp_setup_irq(int periphid, irq_priority_t priority,
irq_trigger_t type)
return cpuint;
}
- irq = ESP_PERIPH2IRQ(periphid);
+ irq = ESP_SOURCE2IRQ(source);
- DEBUGASSERT(periphid >= 0 && periphid < ESP_NPERIPHERALS);
- DEBUGASSERT(cpuint >= ESP_CPUINT_MIN && cpuint <= ESP_CPUINT_MAX);
- DEBUGASSERT(g_cpu_intmap[cpuint] == CPUINT_UNASSIGNED);
+ DEBUGASSERT(source >= 0 && source < ESP_NSOURCES);
+ DEBUGASSERT(cpuint >= 0 && cpuint < ESP_NCPUINTS);
+ DEBUGASSERT(CPUINT_ISFREE(g_cpuint_map[cpuint]));
- CPUINT_ASSIGN(g_cpu_intmap[cpuint], irq);
- g_irqmap[irq] = cpuint;
+ CPUINT_ASSIGN(g_cpuint_map[cpuint], irq);
+ g_irq_map[irq] = cpuint;
- esp_bind_irq(cpuint, periphid, priority, type);
+ esp_bind_irq(cpuint, source, priority, type);
leave_critical_section(irqstate);
@@ -481,13 +467,13 @@ int esp_setup_irq(int periphid, irq_priority_t priority,
irq_trigger_t type)
*
* Description:
* This function undoes the operations done by esp_setup_irq.
- * It detaches a peripheral interrupt from a CPU interrupt and frees the
+ * It detaches a interrupt source from a CPU interrupt and frees the
* CPU interrupt.
*
* Input Parameters:
- * periphid - The peripheral number from irq.h to be detached from the
+ * source - The interrupt source from irq.h to be detached from the
* CPU interrupt.
- * cpuint - The CPU interrupt from which the peripheral interrupt
+ * cpuint - The CPU interrupt from which the interrupt source
* will be detached.
*
* Returned Value:
@@ -495,7 +481,7 @@ int esp_setup_irq(int periphid, irq_priority_t priority,
irq_trigger_t type)
*
****************************************************************************/
-void esp_teardown_irq(int periphid, int cpuint)
+void esp_teardown_irq(int source, int cpuint)
{
irqstate_t irqstate;
int irq;
@@ -504,21 +490,19 @@ void esp_teardown_irq(int periphid, int cpuint)
/* Tearing down an IRQ includes the following steps:
* 1. Free the previously allocated CPU interrupt.
- * 2. Detach the interrupt from the peripheral.
+ * 2. Detach the CPU interrupt from the interrupt source.
* 3. Unmap the IRQ from the IRQ-to-cpuint map.
*/
- esp_free_cpuint(cpuint);
+ esp_cpuint_free(cpuint);
- irq = ESP_PERIPH2IRQ(periphid);
+ irq = ESP_SOURCE2IRQ(source);
- DEBUGASSERT(periphid >= 0 && periphid < ESP_NPERIPHERALS);
+ DEBUGASSERT(source >= 0 && source < ESP_NSOURCES);
- DEBUGASSERT(g_cpu_intmap[cpuint] != CPUINT_UNASSIGNED);
- g_cpu_intmap[cpuint] = CPUINT_UNASSIGNED;
- g_irqmap[irq] = IRQ_UNMAPPED;
+ g_irq_map[irq] = IRQ_UNMAPPED;
- putreg32(NO_CPUINT, CORE0_PERIPH_REG(periphid));
+ esp_rom_route_intr_matrix(PRO_CPU_NUM, source, NO_CPUINT);
leave_critical_section(irqstate);
}
@@ -541,37 +525,26 @@ void esp_teardown_irq(int periphid, int cpuint)
IRAM_ATTR uintptr_t *riscv_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
{
int irq;
- uint8_t cpuint = mcause & RISCV_IRQ_MASK;
bool is_irq = (RISCV_IRQ_BIT & mcause) != 0;
-
-#ifdef CONFIG_ESPRESSIF_EXCEPTION_ENABLE_CACHE
- if (!is_irq &&
- (mcause != RISCV_IRQ_ECALLM))
- {
- if (!spi_flash_cache_enabled())
- {
- spi_flash_enable_cache(0);
- _err("ERROR: Cache was disabled and re-enabled\n");
- }
- }
-#endif
-
- irqinfo("INFO: mcause=%08" PRIXPTR "\n", mcause);
-
- DEBUGASSERT(cpuint <= ESP_CPUINT_MAX);
-
- irqinfo("INFO: cpuint=%" PRIu8 "\n", cpuint);
+ bool is_edge = false;
if (is_irq)
{
- irq = CPUINT_GETIRQ(g_cpu_intmap[cpuint]);
+ uint8_t cpuint = mcause & RISCV_IRQ_MASK;
- DEBUGASSERT(CPUINT_GETEN(g_cpu_intmap[cpuint]) != 0);
- DEBUGASSERT(irq != CPUINT_UNASSIGNED);
+ DEBUGASSERT(cpuint >= 0 && cpuint < ESP_NCPUINTS);
+ DEBUGASSERT(CPUINT_ISENABLED(g_cpuint_map[cpuint]));
+ DEBUGASSERT(CPUINT_ISASSIGNED(g_cpuint_map[cpuint]));
- /* Clear edge interrupts. */
+ irq = g_cpuint_map[cpuint].irq;
- putreg32(UINT32_C(1) << cpuint, INTERRUPT_CORE0_CPU_INT_CLEAR_REG);
+ is_edge = esprv_intc_int_get_type(cpuint) == INTR_TYPE_EDGE;
+ if (is_edge)
+ {
+ /* Clear edge interrupts. */
+
+ esp_cpu_intr_edge_ack(cpuint);
+ }
}
else
{
@@ -580,15 +553,13 @@ IRAM_ATTR uintptr_t *riscv_dispatch_irq(uintptr_t mcause,
uintptr_t *regs)
irq = mcause;
}
- irqinfo("INFO: IRQ=%d\n", irq);
-
regs = riscv_doirq(irq, regs);
/* Toggle the bit back to zero. */
- if (is_irq)
+ if (is_edge)
{
- putreg32(0, INTERRUPT_CORE0_CPU_INT_CLEAR_REG);
+ esp_cpu_intr_edge_ack(0);
}
return regs;
diff --git a/arch/risc-v/src/espressif/esp_irq.h
b/arch/risc-v/src/espressif/esp_irq.h
index 9bdb6ecd72..99573c065a 100644
--- a/arch/risc-v/src/espressif/esp_irq.h
+++ b/arch/risc-v/src/espressif/esp_irq.h
@@ -87,35 +87,18 @@ typedef enum irq_priority_e
*
* Input Parameters:
* cpuint - CPU interrupt ID.
- * periphid - Peripheral ID.
+ * source - Interrupt source.
* priority - Interrupt priority.
- * flags - Interrupt flags.
+ * type - Interrupt trigger type.
*
* Returned Value:
* None.
*
****************************************************************************/
-void esp_bind_irq(int cpuint, int periphid, irq_priority_t priority,
+void esp_bind_irq(int cpuint, int source, irq_priority_t priority,
irq_trigger_t type);
-/****************************************************************************
- * Name: esp_cpuint_initialize
- *
- * Description:
- * Initialize CPU interrupts.
- *
- * Input Parameters:
- * None.
- *
- * Returned Value:
- * Zero (OK) is returned on success; A negated errno value is returned on
- * any failure.
- *
- ****************************************************************************/
-
-int esp_cpuint_initialize(void);
-
/****************************************************************************
* Name: esp_setup_irq
*
@@ -124,7 +107,7 @@ int esp_cpuint_initialize(void);
* priority and type and attaches it to the given peripheral.
*
* Input Parameters:
- * periphid - The peripheral number from irq.h to be assigned to
+ * source - The interrupt source from irq.h to be assigned to
* a CPU interrupt.
* priority - Interrupt priority.
* type - Interrupt trigger type.
@@ -135,7 +118,7 @@ int esp_cpuint_initialize(void);
*
****************************************************************************/
-int esp_setup_irq(int periphid, irq_priority_t priority, irq_trigger_t type);
+int esp_setup_irq(int source, irq_priority_t priority, irq_trigger_t type);
/****************************************************************************
* Name: esp_teardown_irq
@@ -146,7 +129,7 @@ int esp_setup_irq(int periphid, irq_priority_t priority,
irq_trigger_t type);
* CPU interrupt.
*
* Input Parameters:
- * periphid - The peripheral number from irq.h to be detached from the
+ * source - The interrupt source from irq.h to be detached from the
* CPU interrupt.
* cpuint - The CPU interrupt from which the peripheral interrupt
* will be detached.
@@ -156,7 +139,7 @@ int esp_setup_irq(int periphid, irq_priority_t priority,
irq_trigger_t type);
*
****************************************************************************/
-void esp_teardown_irq(int periphid, int cpuint);
+void esp_teardown_irq(int source, int cpuint);
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/risc-v/src/espressif/esp_lowputc.c
b/arch/risc-v/src/espressif/esp_lowputc.c
index 4f1ef3eb8b..87fd53b263 100644
--- a/arch/risc-v/src/espressif/esp_lowputc.c
+++ b/arch/risc-v/src/espressif/esp_lowputc.c
@@ -67,7 +67,7 @@ static uart_hal_context_t g_uart0_hal =
struct esp_uart_s g_uart0_config =
{
- .periphid = ESP_PERIPH_UART0,
+ .source = UART0_INTR_SOURCE,
.cpuint = -ENOMEM,
.int_pri = ESP_IRQ_PRIORITY_DEFAULT,
.id = 0,
@@ -112,7 +112,7 @@ static uart_hal_context_t g_uart1_hal =
struct esp_uart_s g_uart1_config =
{
- .periphid = ESP_PERIPH_UART1,
+ .source = UART1_INTR_SOURCE,
.cpuint = -ENOMEM,
.int_pri = ESP_IRQ_PRIORITY_DEFAULT,
.id = 1,
diff --git a/arch/risc-v/src/espressif/esp_lowputc.h
b/arch/risc-v/src/espressif/esp_lowputc.h
index 4f450d1878..a20842e64b 100644
--- a/arch/risc-v/src/espressif/esp_lowputc.h
+++ b/arch/risc-v/src/espressif/esp_lowputc.h
@@ -50,7 +50,7 @@
struct esp_uart_s
{
- int periphid; /* UART peripheral ID */
+ int source; /* UART interrupt source */
int cpuint; /* CPU interrupt assigned to this UART */
irq_priority_t int_pri; /* UART Interrupt Priority */
int id; /* UART ID */
diff --git a/arch/risc-v/src/espressif/esp_serial.c
b/arch/risc-v/src/espressif/esp_serial.c
index 6d024dacd0..a9cb598cfb 100644
--- a/arch/risc-v/src/espressif/esp_serial.c
+++ b/arch/risc-v/src/espressif/esp_serial.c
@@ -140,20 +140,20 @@ static bool esp_rxflowcontrol(uart_dev_t *dev,
static struct uart_ops_s g_uart_ops =
{
- .setup = esp_setup,
- .shutdown = esp_shutdown,
- .attach = esp_attach,
- .detach = esp_detach,
- .txint = esp_txint,
- .rxint = esp_rxint,
- .rxavailable = esp_rxavailable,
- .txready = esp_txready,
- .txempty = esp_txempty,
- .send = esp_send,
- .receive = esp_receive,
- .ioctl = esp_ioctl,
+ .setup = esp_setup,
+ .shutdown = esp_shutdown,
+ .attach = esp_attach,
+ .detach = esp_detach,
+ .txint = esp_txint,
+ .rxint = esp_rxint,
+ .rxavailable = esp_rxavailable,
+ .txready = esp_txready,
+ .txempty = esp_txempty,
+ .send = esp_send,
+ .receive = esp_receive,
+ .ioctl = esp_ioctl,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
- .rxflowcontrol = esp_rxflowcontrol,
+ .rxflowcontrol = esp_rxflowcontrol
#endif
};
@@ -280,7 +280,7 @@ static int uart_handler(int irq, void *context, void *arg)
}
/****************************************************************************
- * Name: esp_serial_set_data_length
+ * Name: set_data_length
*
* Description:
* Set the data bits length, according to the value in the private driver
@@ -290,31 +290,23 @@ static int uart_handler(int irq, void *context, void *arg)
* priv - Pointer to the private driver struct.
*
* Returned Value:
- * Zero on success; a negated errno value on failure.
+ * None.
*
****************************************************************************/
-static int esp_serial_set_data_length(const struct esp_uart_s *priv)
+static void set_data_length(const struct esp_uart_s *priv)
{
- int ret = OK;
uint32_t length = (priv->bits - 5);
/* If it is the allowed range */
- if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS)
- {
- uart_hal_set_data_bit_num(priv->hal, length);
- }
- else
- {
- ret = -EINVAL;
- }
+ DEBUGASSERT(length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS);
- return ret;
+ uart_hal_set_data_bit_num(priv->hal, length);
}
/****************************************************************************
- * Name: esp_serial_set_stop_length
+ * Name: set_stop_length
*
* Description:
* Set the stop bits length, according to the value in the private driver
@@ -328,16 +320,20 @@ static int esp_serial_set_data_length(const struct
esp_uart_s *priv)
*
****************************************************************************/
-static void esp_serial_set_stop_length(const struct esp_uart_s *priv)
+static void set_stop_length(const struct esp_uart_s *priv)
{
+ uart_stop_bits_t stop_bits;
+
if (priv->stop_b2)
{
- uart_hal_set_stop_bits(priv->hal, UART_STOP_BITS_2);
+ stop_bits = UART_STOP_BITS_2;
}
else
{
- uart_hal_set_stop_bits(priv->hal, UART_STOP_BITS_1);
+ stop_bits = UART_STOP_BITS_1;
}
+
+ uart_hal_set_stop_bits(priv->hal, stop_bits);
}
/****************************************************************************
@@ -365,55 +361,34 @@ static int esp_setup(uart_dev_t *dev)
struct esp_uart_s *priv = dev->priv;
uint32_t sclk_freq;
- uart_hal_init(priv->hal, priv->id);
-
- /* Initialize UART module */
-
- /* Discard corrupt RX data and
- * disable UART memory clock gate enable signal.
- */
-
- priv->hal->dev->conf0.err_wr_mask = 0;
- priv->hal->dev->conf0.mem_clk_en = 1;
-
- /* Define 0 as the threshold that means TX FIFO buffer is empty. */
-
- uart_hal_set_txfifo_empty_thr(priv->hal, 0);
-
- /* Define a threshold to trigger an RX FIFO FULL interrupt.
- * Define just one byte to read data immediately.
- */
-
- uart_hal_set_rxfifo_full_thr(priv->hal, 1);
-
- /* Define the maximum FIFO size for RX and TX FIFO.
- * That means, 1 block = 128 bytes.
- * As a consequence, software serial FIFO can unload the bytes and
- * not wait too much on polling activity.
- */
-
- priv->hal->dev->mem_conf.tx_size = 1;
- priv->hal->dev->mem_conf.rx_size = 1;
-
/* Enable the UART Clock */
esp_lowputc_enable_sysclk(priv);
- uart_hal_set_sclk(priv->hal, UART_SCLK_APB);
- clk_tree_src_get_freq_hz(SOC_MOD_CLK_APB,
+ clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_DEFAULT,
CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&sclk_freq);
+
+ /* Initialize UART module */
+
+ uart_hal_init(priv->hal, priv->id);
+ uart_hal_set_mode(priv->hal, UART_MODE_UART);
+ uart_hal_set_sclk(priv->hal, UART_SCLK_DEFAULT);
uart_hal_set_baudrate(priv->hal, priv->baud, sclk_freq);
uart_hal_set_parity(priv->hal, priv->parity);
+ set_data_length(priv);
+ set_stop_length(priv);
uart_hal_set_tx_idle_num(priv->hal, 0);
- /* Data Frame size */
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
- esp_serial_set_data_length(priv);
+ uart_hal_set_txfifo_empty_thr(priv->hal, 10);
- /* Stop bit */
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
- esp_serial_set_stop_length(priv);
+ uart_hal_set_rxfifo_full_thr(priv->hal, 120);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || \
defined(CONFIG_SERIAL_OFLOWCONTROL)
@@ -514,7 +489,7 @@ static int esp_attach(uart_dev_t *dev)
/* Set up to receive peripheral interrupts */
- priv->cpuint = esp_setup_irq(priv->periphid, priv->int_pri,
+ priv->cpuint = esp_setup_irq(priv->source, priv->int_pri,
ESP_IRQ_TRIGGER_LEVEL);
if (priv->cpuint < 0)
{
@@ -565,7 +540,7 @@ static void esp_detach(uart_dev_t *dev)
/* Disassociate the peripheral interrupt from the CPU interrupt */
- esp_teardown_irq(priv->periphid, priv->cpuint);
+ esp_teardown_irq(priv->source, priv->cpuint);
priv->cpuint = -ENOMEM;
}
@@ -631,7 +606,7 @@ static void esp_rxint(uart_dev_t *dev, bool enable)
* NOTE: RX timeout feature needs to be enabled.
*/
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
- uart_hal_set_rx_timeout(priv->hal, 0x16);
+ uart_hal_set_rx_timeout(priv->hal, 0xa);
uart_hal_ena_intr_mask(priv->hal, ints_mask);
#endif
}
diff --git a/arch/risc-v/src/espressif/esp_timerisr.c
b/arch/risc-v/src/espressif/esp_timerisr.c
index b6a4baddc0..7b9d7a9196 100644
--- a/arch/risc-v/src/espressif/esp_timerisr.c
+++ b/arch/risc-v/src/espressif/esp_timerisr.c
@@ -39,6 +39,12 @@
#include "periph_ctrl.h"
#include "systimer.h"
+#if SOC_SYSTIMER_INT_LEVEL
+# define SYSTIMER_TRIGGER_TYPE ESP_IRQ_TRIGGER_LEVEL
+#else
+# define SYSTIMER_TRIGGER_TYPE ESP_IRQ_TRIGGER_EDGE
+#endif /* SOC_SYSTIMER_INT_LEVEL */
+
/****************************************************************************
* Private Data
****************************************************************************/
@@ -131,14 +137,17 @@ void up_timer_initialize(void)
SYSTIMER_ALARM_OS_TICK_CORE0);
systimer_hal_enable_counter(&systimer_hal, SYSTIMER_COUNTER_OS_TICK);
- esp_setup_irq(ESP_PERIPH_SYSTIMER_T0, ESP_IRQ_PRIORITY_DEFAULT,
- ESP_IRQ_TRIGGER_LEVEL);
+ esp_setup_irq(SYSTIMER_TARGET0_EDGE_INTR_SOURCE,
+ ESP_IRQ_PRIORITY_DEFAULT,
+ SYSTIMER_TRIGGER_TYPE);
/* Attach the timer interrupt. */
- irq_attach(ESP_IRQ_SYSTIMER_T0, (xcpt_t)systimer_irq_handler, NULL);
+ irq_attach(ESP_IRQ_SYSTIMER_TARGET0_EDGE,
+ (xcpt_t)systimer_irq_handler,
+ NULL);
/* Enable the allocated CPU interrupt. */
- up_enable_irq(ESP_IRQ_SYSTIMER_T0);
+ up_enable_irq(ESP_IRQ_SYSTIMER_TARGET0_EDGE);
}
diff --git a/arch/risc-v/src/espressif/hal_esp32c6.mk
b/arch/risc-v/src/espressif/hal_esp32c6.mk
new file mode 100644
index 0000000000..c2819c77a5
--- /dev/null
+++ b/arch/risc-v/src/espressif/hal_esp32c6.mk
@@ -0,0 +1,96 @@
+############################################################################
+# arch/risc-v/src/espressif/esp32c6.mk
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Include header paths
+
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/driver/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/efuse/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/efuse/private_include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/efuse/$(CHIP_SERIES)/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/efuse/$(CHIP_SERIES)/private_include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_common/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/include/esp_private
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/include/soc
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/$(CHIP_SERIES)
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/$(CHIP_SERIES)/private_include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_rom/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_rom/include/$(CHIP_SERIES)
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_rom/$(CHIP_SERIES)
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_system/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_system/port/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_system/port/include/private/esp_private
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_system/port/public_compat
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/$(CHIP_SERIES)/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/platform_port/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/log
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/log/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/riscv/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/soc/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/soc/$(CHIP_SERIES)/include
+INCLUDES +=
$(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/nuttx/$(CHIP_SERIES)/include
+
+# Linker scripts
+
+ARCHSCRIPT +=
$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.ld
+ARCHSCRIPT +=
$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.api.ld
+ARCHSCRIPT +=
$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.newlib.ld
+ARCHSCRIPT +=
$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.version.ld
+ARCHSCRIPT +=
$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.spiflash.ld
+ARCHSCRIPT +=
$(ARCH_SRCDIR)/chip/$(HAL_ESPRESSIF_UNPACK)/components/soc/$(CHIP_SERIES)/ld/$(CHIP_SERIES).peripherals.ld
+
+# Source files
+
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/efuse/src/esp_efuse_api.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/efuse/src/esp_efuse_utility.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/efuse/$(CHIP_SERIES)/esp_efuse_fields.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/efuse/$(CHIP_SERIES)/esp_efuse_table.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/efuse/$(CHIP_SERIES)/esp_efuse_utility.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/cpu.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/esp_clk.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/modem_clock.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/periph_ctrl.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/regi2c_ctrl.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/clk_tree_common.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/$(CHIP_SERIES)/clk_tree.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_init.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_param.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_time.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/$(CHIP_SERIES)/sar_periph_ctrl.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_hw_support/port/$(CHIP_SERIES)/systimer.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_rom/patches/esp_rom_regi2c_$(CHIP_SERIES).c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_system/port/brownout.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/esp_system/port/soc/$(CHIP_SERIES)/clk.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/brownout_hal.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/efuse_hal.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/systimer_hal.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/uart_hal.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/uart_hal_iram.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/wdt_hal_iram.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/$(CHIP_SERIES)/clk_tree_hal.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/$(CHIP_SERIES)/efuse_hal.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/hal/$(CHIP_SERIES)/modem_clock_hal.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/log/log.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/log/log_noos.c
+CHIP_CSRCS += chip/$(HAL_ESPRESSIF_UNPACK)/components/riscv/interrupt.c
+CHIP_CSRCS +=
chip/$(HAL_ESPRESSIF_UNPACK)/components/soc/$(CHIP_SERIES)/gpio_periph.c
diff --git a/boards/Kconfig b/boards/Kconfig
index 7a339937df..d34b87b658 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -411,6 +411,12 @@ config ARCH_BOARD_ESP32S3_EYE
featuring the ESP32-S3 CPU with a 2-Megapixel camera, an LCD
display,
a microphone, an 8 MB Octal PSRAM and an 8 MB flash.
+config ARCH_BOARD_ESP32C6_GENERIC
+ bool "Espressif ESP32-C6 Generic DevKit"
+ depends on ESPRESSIF_ESP32C6
+ ---help---
+ The ESP32-C6 DevKit features the ESP32-C6 CPU with a RISC-V
core.
+
config ARCH_BOARD_ET_STM32_STAMP
bool "Futurlec: ET-STM32 Stamp"
depends on ARCH_CHIP_STM32F103RE
@@ -2769,6 +2775,7 @@ config ARCH_BOARD
default "esp32s3-devkit" if ARCH_BOARD_ESP32S3_DEVKIT
default "esp32s3-eye" if ARCH_BOARD_ESP32S3_EYE
default "esp32c6-devkit" if ARCH_BOARD_ESP32C6_DEVKIT
+ default "esp32c6-generic" if ARCH_BOARD_ESP32C6_GENERIC
default "et-stm32-stamp" if ARCH_BOARD_ET_STM32_STAMP
default "tlsr8278adk80d" if ARCH_BOARD_TLSR8278ADK80D
default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG
@@ -3756,6 +3763,9 @@ endif
if ARCH_BOARD_ESP32C6_DEVKIT
source "boards/risc-v/esp32c6/esp32c6-devkit/Kconfig"
endif
+if ARCH_BOARD_ESP32C6_GENERIC
+source "boards/risc-v/espressif/esp32c6-generic/Kconfig"
+endif
if ARCH_BOARD_SIM
source "boards/sim/sim/sim/Kconfig"
endif
diff --git a/boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld
b/boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld
index 9202d3339b..e20d0a9797 100644
--- a/boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld
+++ b/boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld
@@ -36,15 +36,18 @@ SECTIONS
*(.iram1)
*(.iram1.*)
- *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*)
- *libarch.a:rtc_.*(.text .text.* .literal .literal.*)
*libarch.a:brownout.*(.text .text.* .literal .literal.*)
-
- *(.wifi0iram .wifi0iram.*)
- *(.wifirxiram .wifirxiram.*)
- *(.wifislpiram .wifislpiram.*)
- *(.wifislprxiram .wifislprxiram.*)
-
+ *libarch.a:cpu.*(.text .text.* .literal .literal.*)
+ *libarch.a:gpio_hal.*(.text .text.* .literal .literal.*)
+ *libarch.a:periph_ctrl.*(.text .text.* .literal .literal.*)
+ *libarch.a:rtc_clk.*(.text .text.* .literal .literal.*)
+ *libarch.a:rtc_sleep.*(.text .text.* .literal .literal.*)
+ *libarch.a:rtc_time.*(.text .text.* .literal .literal.*)
+ *libarch.a:systimer.*(.text .text.* .literal .literal.*)
+ *libarch.a:systimer_hal.*(.text .text.* .literal .literal.*)
+ *libarch.a:uart_hal_iram.*(.text .text.* .literal .literal.*)
+ *libarch.a:wdt_hal_iram.*(.text .text.* .literal .literal.*)
+ *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*)
} >iram0_0_seg
/* This section is required to skip .iram0.text area because iram0_0_seg
@@ -108,6 +111,19 @@ SECTIONS
*(.jcr)
*(.dram1)
*(.dram1.*)
+
+ *libarch.a:brownout.*(.rodata .rodata.*)
+ *libarch.a:cpu.*(.rodata .rodata.*)
+ *libarch.a:gpio_hal.*(.rodata .rodata.*)
+ *libarch.a:periph_ctrl.*(.rodata .rodata.*)
+ *libarch.a:rtc_clk.*(.rodata .rodata.*)
+ *libarch.a:rtc_sleep.*(.rodata .rodata.*)
+ *libarch.a:rtc_time.*(.rodata .rodata.*)
+ *libarch.a:systimer.*(.rodata .rodata.*)
+ *libarch.a:systimer_hal.*(.rodata .rodata.*)
+ *libarch.a:uart_hal_iram.*(.rodata .rodata.*)
+ *libarch.a:wdt_hal_iram.*(.rodata .rodata.*)
+ *libsched.a:irq_dispatch.*(.rodata .rodata.*)
. = ALIGN(4);
_edata = ABSOLUTE(.);
@@ -137,9 +153,20 @@ SECTIONS
.flash_rodata_dummy (NOLOAD):
{
- . = SIZEOF(.flash.text);
+ /* Start at the same alignment constraint than .flash.text */
+
+ . = ALIGN(ALIGNOF(.flash.text));
+
+ /* Create an empty gap as big as .flash.text section */
+
+ . = . + SIZEOF(.flash.text);
+
+ /* Prepare the alignment of the section above. Few bytes (0x20) must be
+ * added for the mapping header.
+ */
+
. = ALIGN(0x10000) + 0x20;
- } >drom0_0_seg
+ } >default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
diff --git a/boards/risc-v/espressif/common/scripts/esp32c6_aliases.ld
b/boards/risc-v/espressif/common/scripts/esp32c6_aliases.ld
new file mode 100644
index 0000000000..29335e191c
--- /dev/null
+++ b/boards/risc-v/espressif/common/scripts/esp32c6_aliases.ld
@@ -0,0 +1,29 @@
+/****************************************************************************
+ * boards/risc-v/espressif/common/scripts/esp32c6_aliases.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_BLE
+
+/* Lower-case aliases for BLE library symbols not compliant to nxstyle */
+
+api_vhci_host_check_send_available = API_vhci_host_check_send_available;
+api_vhci_host_send_packet = API_vhci_host_send_packet;
+api_vhci_host_register_callback = API_vhci_host_register_callback;
+
+#endif
diff --git a/boards/risc-v/espressif/common/scripts/esp32c6_flat_memory.ld
b/boards/risc-v/espressif/common/scripts/esp32c6_flat_memory.ld
new file mode 100644
index 0000000000..07cfb9f823
--- /dev/null
+++ b/boards/risc-v/espressif/common/scripts/esp32c6_flat_memory.ld
@@ -0,0 +1,109 @@
+/****************************************************************************
+ * boards/risc-v/espressif/common/scripts/esp32c6_flat_memory.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * ESP32-C6 Linker Script Memory Layout
+ *
+ * This file describes the memory layout (memory blocks) as virtual
+ * memory addresses.
+ *
+ * esp32c6_<legacy/mcuboot>_sections.ld contains output sections to link
compiler
+ * output into these memory blocks.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#define SRAM_IRAM_START 0x40800000
+#define SRAM_DRAM_START 0x40800000
+
+#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
+
+/* 2nd stage bootloader iram_loader_seg start address */
+
+#define SRAM_DRAM_END 0x40880000 - I_D_SRAM_OFFSET
+
+#define SRAM_IRAM_ORG (SRAM_IRAM_START)
+#define SRAM_DRAM_ORG (SRAM_DRAM_START)
+
+#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
+
+/* IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB */
+
+#define CONFIG_MMU_PAGE_SIZE 0x10000
+#define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8)
+
+#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
+
+MEMORY
+{
+ /* Below values assume the flash cache is on, and have the blocks this
+ * uses subtracted from the length of the various regions. The 'data access
+ * port' dram/drom regions map to the same iram/irom regions but are
+ * connected to the data port of the CPU and e.g. allow bytewise access.
+ */
+
+ iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
+
+ /* Flash mapped instruction data.
+ *
+ * The 0x20 offset is a convenience for the app binary image generation.
+ * Flash cache has 64KB pages. The .bin file which is flashed to the chip
+ * has a 0x18 byte file header, and each segment has a 0x08 byte segment
+ * header. Setting this offset makes it simple to meet the flash cache MMU's
+ * constraint that (paddr % 64KB == vaddr % 64KB).
+ */
+
+ irom_seg (RX) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
+
+ /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
+ * Enabling Bluetooth & Trace Memory features in menuconfig will decrease
+ * the amount of RAM available.
+ */
+
+ dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
+
+ /* Flash mapped constant data */
+
+ drom_seg (R) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
+
+ /* RTC fast memory (executable). Persists over deep sleep. */
+
+ lp_ram_seg (RWX) : org = 0x50000000, len = 0x4000
+}
+
+/* The lines below define location alias for .rtc.data section
+ * ESP32-C6 has no distinguished LP(RTC) fast and slow memory sections,
+ * instead, there is a unified LP_RAM section.
+ * Thus, the following region segments are not configurable like on other
targets
+ */
+
+REGION_ALIAS("rtc_iram_seg", lp_ram_seg);
+REGION_ALIAS("rtc_data_seg", rtc_iram_seg);
+REGION_ALIAS("rtc_slow_seg", rtc_iram_seg);
+REGION_ALIAS("rtc_data_location", rtc_iram_seg);
+
+#if CONFIG_ESPRESSIF_RUN_IRAM
+ REGION_ALIAS("default_rodata_seg", dram0_0_seg);
+ REGION_ALIAS("default_code_seg", iram0_0_seg);
+#else
+ REGION_ALIAS("default_rodata_seg", drom_seg);
+ REGION_ALIAS("default_code_seg", irom_seg);
+#endif /* CONFIG_ESPRESSIF_RUN_IRAM */
diff --git a/boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld
b/boards/risc-v/espressif/common/scripts/esp32c6_legacy_sections.ld
similarity index 74%
copy from boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld
copy to boards/risc-v/espressif/common/scripts/esp32c6_legacy_sections.ld
index 9202d3339b..b19ef6a07f 100644
--- a/boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld
+++ b/boards/risc-v/espressif/common/scripts/esp32c6_legacy_sections.ld
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld
+ * boards/risc-v/espressif/common/scripts/esp32c6_legacy_sections.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -36,15 +36,42 @@ SECTIONS
*(.iram1)
*(.iram1.*)
- *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*)
- *libarch.a:rtc_.*(.text .text.* .literal .literal.*)
*libarch.a:brownout.*(.text .text.* .literal .literal.*)
+ *libarch.a:cpu.*(.text .text.* .literal .literal.*)
+ *libarch.a:gpio_hal.*(.text .text.* .literal .literal.*)
+ *libarch.a:periph_ctrl.*(.text .text.* .literal .literal.*)
+ *libarch.a:rtc_clk.*(.text .text.* .literal .literal.*)
+ *libarch.a:rtc_sleep.*(.text .text.* .literal .literal.*)
+ *libarch.a:rtc_time.*(.text .text.* .literal .literal.*)
+ *libarch.a:systimer.*(.text .text.* .literal .literal.*)
+ *libarch.a:systimer_hal.*(.text .text.* .literal .literal.*)
+ *libarch.a:uart_hal_iram.*(.text .text.* .literal .literal.*)
+ *libarch.a:wdt_hal_iram.*(.text .text.* .literal .literal.*)
+ *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*)
+ } >iram0_0_seg
+
+ /* Marks the end of IRAM code segment */
+
+ .iram0.text_end (NOLOAD) :
+ {
+ . = ALIGN(16);
+ } >iram0_0_seg
+
+ .iram0.data :
+ {
+ . = ALIGN(16);
+ *(.iram.data)
+ *(.iram.data*)
+ } >iram0_0_seg
- *(.wifi0iram .wifi0iram.*)
- *(.wifirxiram .wifirxiram.*)
- *(.wifislpiram .wifislpiram.*)
- *(.wifislprxiram .wifislprxiram.*)
+ .iram0.bss (NOLOAD) :
+ {
+ . = ALIGN(16);
+ *(.iram.bss)
+ *(.iram.bss*)
+ . = ALIGN(16);
+ _iram_end = ABSOLUTE(.);
} >iram0_0_seg
/* This section is required to skip .iram0.text area because iram0_0_seg
@@ -60,7 +87,7 @@ SECTIONS
.dram0.bss (NOLOAD) :
{
- . = ALIGN (8);
+ . = ALIGN(8);
_sbss = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
@@ -77,7 +104,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
- . = ALIGN (8);
+ . = ALIGN(8);
_ebss = ABSOLUTE(.);
} >dram0_0_seg
@@ -87,8 +114,10 @@ SECTIONS
* or during the application's initialization sequence.
*/
+ . = ALIGN(4);
*(.noinit)
*(.noinit.*)
+ . = ALIGN(4);
} >dram0_0_seg
.dram0.data :
@@ -108,6 +137,20 @@ SECTIONS
*(.jcr)
*(.dram1)
*(.dram1.*)
+
+ *libarch.a:brownout.*(.rodata .rodata.*)
+ *libarch.a:cpu.*(.rodata .rodata.*)
+ *libarch.a:gpio_hal.*(.rodata .rodata.*)
+ *libarch.a:interrupt.*(.rodata .rodata.*)
+ *libarch.a:periph_ctrl.*(.rodata .rodata.*)
+ *libarch.a:rtc_clk.*(.rodata .rodata.*)
+ *libarch.a:rtc_sleep.*(.rodata .rodata.*)
+ *libarch.a:rtc_time.*(.rodata .rodata.*)
+ *libarch.a:systimer.*(.rodata .rodata.*)
+ *libarch.a:systimer_hal.*(.rodata .rodata.*)
+ *libarch.a:uart_hal_iram.*(.rodata .rodata.*)
+ *libarch.a:wdt_hal_iram.*(.rodata .rodata.*)
+ *libsched.a:irq_dispatch.*(.rodata .rodata.*)
. = ALIGN(4);
_edata = ABSOLUTE(.);
@@ -137,9 +180,20 @@ SECTIONS
.flash_rodata_dummy (NOLOAD):
{
- . = SIZEOF(.flash.text);
+ /* Start at the same alignment constraint than .flash.text */
+
+ . = ALIGN(ALIGNOF(.flash.text));
+
+ /* Create an empty gap as big as .flash.text section */
+
+ . = . + SIZEOF(.flash.text);
+
+ /* Prepare the alignment of the section above. Few bytes (0x20) must be
+ * added for the mapping header.
+ */
+
. = ALIGN(0x10000) + 0x20;
- } >drom0_0_seg
+ } >default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
@@ -198,53 +252,22 @@ SECTIONS
. = ALIGN(4);
} >default_rodata_seg
- /* Marks the end of IRAM code segment */
-
- .iram0.text_end (NOLOAD) :
- {
- . = ALIGN (16);
- } >iram0_0_seg
-
- .iram0.data :
- {
- . = ALIGN(16);
- *(.iram.data)
- *(.iram.data*)
- } >iram0_0_seg
-
- .iram0.bss (NOLOAD) :
- {
- . = ALIGN(16);
- *(.iram.bss)
- *(.iram.bss*)
-
- . = ALIGN(16);
- _iram_end = ABSOLUTE(.);
- } >iram0_0_seg
-
/* RTC fast memory holds RTC wake stub code !*/
.rtc.text :
{
. = ALIGN(4);
*(.rtc.literal .rtc.text)
- } >rtc_seg
+ } >lp_ram_seg
/* This section is required to skip rtc.text area because the text and
- * data segments reflect the same address space on different buses.
+ * data segements reflect the same address space on different buses.
*/
.rtc.dummy :
{
. = SIZEOF(.rtc.text);
- } >rtc_seg
-
- /* RTC BSS section. */
-
- .rtc.bss (NOLOAD) :
- {
- *(.rtc.bss)
- } >rtc_seg
+ } >lp_ram_seg
/* RTC data section holds RTC wake stub data/rodata. */
@@ -252,11 +275,6 @@ SECTIONS
{
*(.rtc.data)
*(.rtc.rodata)
-
- /* Whatever is left from the RTC memory is used as a special heap. */
-
- _srtcheap = ABSOLUTE(.);
-
- } >rtc_seg
+ } >lp_ram_seg
}
diff --git a/boards/risc-v/espressif/esp32c6-generic/Kconfig
b/boards/risc-v/espressif/esp32c6-generic/Kconfig
new file mode 100644
index 0000000000..b8f2c2b023
--- /dev/null
+++ b/boards/risc-v/espressif/esp32c6-generic/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_ESP32C6_GENERIC
+
+endif # ARCH_BOARD_ESP32C6_GENERIC
diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/nsh/defconfig
b/boards/risc-v/espressif/esp32c6-generic/configs/nsh/defconfig
new file mode 100644
index 0000000000..f20806dc3d
--- /dev/null
+++ b/boards/risc-v/espressif/esp32c6-generic/configs/nsh/defconfig
@@ -0,0 +1,57 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed
.config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that
includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c6-generic"
+CONFIG_ARCH_BOARD_COMMON=y
+CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y
+CONFIG_ARCH_CHIP="espressif"
+CONFIG_ARCH_CHIP_ESPRESSIF=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_ASSERTIONS=y
+CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y
+CONFIG_DEBUG_ERROR=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_WARN=y
+CONFIG_DEV_ZERO=y
+CONFIG_ESPRESSIF_ESP32C6=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_NDEBUG=y
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_BACKTRACE=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_DUMPSTACK=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TESTING_GETPRIME=y
+CONFIG_TESTING_OSTEST=y
+CONFIG_UART0_SERIAL_CONSOLE=y
diff --git a/boards/risc-v/espressif/esp32c6-generic/include/board.h
b/boards/risc-v/espressif/esp32c6-generic/include/board.h
new file mode 100644
index 0000000000..a74c1f40f0
--- /dev/null
+++ b/boards/risc-v/espressif/esp32c6-generic/include/board.h
@@ -0,0 +1,25 @@
+/****************************************************************************
+ * boards/risc-v/espressif/esp32c6-generic/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_INCLUDE_BOARD_H
+#define __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_INCLUDE_BOARD_H
+
+#endif /* __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_INCLUDE_BOARD_H */
+
diff --git a/boards/risc-v/espressif/esp32c6-generic/scripts/Make.defs
b/boards/risc-v/espressif/esp32c6-generic/scripts/Make.defs
new file mode 100644
index 0000000000..792bef6cd7
--- /dev/null
+++ b/boards/risc-v/espressif/esp32c6-generic/scripts/Make.defs
@@ -0,0 +1,60 @@
+############################################################################
+# boards/risc-v/espressif/esp32c6-generic/scripts/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+###########################################################################
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+include $(TOPDIR)/tools/espressif/Config.mk
+include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
+
+# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration
+
+CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES))
+
+# Pick the linker scripts from the board level if they exist, if not
+# pick the common linker scripts.
+
+ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld
+
+ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld)
+ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld)
+
+ARCHPICFLAGS = -fpic
+
+CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES)
$(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS)
$(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+AFLAGS := $(CFLAGS) -D__ASSEMBLY__
+
+# Loadable module definitions
+
+CMODULEFLAGS = $(CFLAGS)
+
+LDMODULEFLAGS = -melf32lriscv -r -e module_initialize
+LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld)
+
+# ELF module definitions
+
+CELFFLAGS = $(CFLAGS)
+CXXELFFLAGS = $(CXXFLAGS)
+
+LDELFFLAGS = -melf32lriscv -r -e main
+LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld)
diff --git a/boards/risc-v/espressif/esp32c6-generic/src/Make.defs
b/boards/risc-v/espressif/esp32c6-generic/src/Make.defs
new file mode 100644
index 0000000000..da0bd0abef
--- /dev/null
+++ b/boards/risc-v/espressif/esp32c6-generic/src/Make.defs
@@ -0,0 +1,31 @@
+#############################################################################
+# boards/risc-v/espressif/esp32c6-generic/src/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+#############################################################################
+
+include $(TOPDIR)/Make.defs
+
+CSRCS = esp32c6_boot.c esp32c6_bringup.c
+
+ifeq ($(CONFIG_BOARDCTL),y)
+ CSRCS += esp32c6_appinit.c
+endif
+
+DEPPATH += --dep-path board
+VPATH += :board
+CFLAGS += $(shell $(INCDIR) "$(CC)"
$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board)
diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6-generic.h
b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6-generic.h
new file mode 100644
index 0000000000..9a008578c0
--- /dev/null
+++ b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6-generic.h
@@ -0,0 +1,72 @@
+/****************************************************************************
+ * boards/risc-v/espressif/esp32c6-generic/src/esp32c6-generic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_SRC_ESP32C6_GENERIC_H
+#define __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_SRC_ESP32C6_GENERIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/compiler.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization.
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y :
+ * Called from the NSH library via board_app_initialize().
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; A negated errno value is returned on
+ * any failure.
+ *
+ ****************************************************************************/
+
+int esp_bringup(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_SRC_ESP32C6_GENERIC_H */
diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_appinit.c
b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_appinit.c
new file mode 100644
index 0000000000..2097b7046b
--- /dev/null
+++ b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_appinit.c
@@ -0,0 +1,81 @@
+/****************************************************************************
+ * boards/risc-v/espressif/esp32c6-generic/src/esp32c6_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+
+#include <nuttx/board.h>
+
+#include "esp32c6-generic.h"
+
+#ifdef CONFIG_BOARDCTL
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value could be such things as a
+ * mode enumeration value, a set of DIP switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+ /* Board initialization already performed by board_late_initialize() */
+
+ return OK;
+#else
+ /* Perform board-specific initialization */
+
+ return esp_bringup();
+#endif
+}
+
+#endif /* CONFIG_BOARDCTL */
diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_boot.c
b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_boot.c
new file mode 100644
index 0000000000..c22b26cd1f
--- /dev/null
+++ b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_boot.c
@@ -0,0 +1,89 @@
+/****************************************************************************
+ * boards/risc-v/espressif/esp32c6-generic/src/esp32c6_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "riscv_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_board_initialize
+ *
+ * Description:
+ * All Espressif boards must provide the following entry point.
+ * This entry point is called early in the initialization -- after all
+ * memory has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_board_initialize(void)
+{
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will
+ * be called immediately after up_initialize() is called and just before
+ * the initial application is started. This additional initialization
+ * phase may be used, for example, to initialize board-specific device
+ * drivers.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
+
+ esp_bringup();
+}
+#endif
diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_bringup.c
b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_bringup.c
new file mode 100644
index 0000000000..47dc889d6f
--- /dev/null
+++ b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_bringup.c
@@ -0,0 +1,100 @@
+/****************************************************************************
+ * boards/risc-v/espressif/esp32c6-generic/src/esp32c6_bringup.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <fcntl.h>
+#include <syslog.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include <nuttx/fs/fs.h>
+
+#include "esp32c6-generic.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization.
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y :
+ * Called from the NSH library via board_app_initialize().
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; A negated errno value is returned on
+ * any failure.
+ *
+ ****************************************************************************/
+
+int esp_bringup(void)
+{
+ int ret;
+
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
+
+ ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_FS_TMPFS
+ /* Mount the tmpfs file system */
+
+ ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n",
+ CONFIG_LIBC_TMPDIR, ret);
+ }
+#endif
+
+ /* If we got here then perhaps not all initialization was successful, but
+ * at least enough succeeded to bring-up NSH with perhaps reduced
+ * capabilities.
+ */
+
+ UNUSED(ret);
+ return OK;
+}
diff --git a/tools/espressif/Config.mk b/tools/espressif/Config.mk
index 8a2c1f275d..2c92c65a8c 100644
--- a/tools/espressif/Config.mk
+++ b/tools/espressif/Config.mk
@@ -56,14 +56,6 @@ else ifeq ($(CONFIG_ESPRESSIF_FLASH_FREQ_20M),y)
FLASH_FREQ := 20m
endif
-ifeq ($(CONFIG_ESPRESSIF_FLASH_DETECT),y)
- ESPTOOL_WRITEFLASH_OPTS := -fs detect -fm dio -ff $(FLASH_FREQ)
-else
- ESPTOOL_WRITEFLASH_OPTS := -fs $(FLASH_SIZE) -fm dio -ff $(FLASH_FREQ)
-endif
-
-ESPTOOL_FLASH_OPTS := -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ)
-
# Configure the variables according to build environment
ifdef ESPTOOL_BINDIR
@@ -95,10 +87,10 @@ define MERGEBIN
exit 1; \
fi
$(Q) if [ -z $(FLASH_SIZE) ]; then \
- echo "Missing Flash memory size configuration for the ESP32-C3
chip."; \
+ echo "Missing Flash memory size configuration."; \
exit 1; \
fi
- esptool.py -c $(CHIP_SERIES) merge_bin --output nuttx.merged.bin
$(ESPTOOL_FLASH_OPTS) $(ESPTOOL_BINS)
+ esptool.py -c $(CHIP_SERIES) merge_bin --output nuttx.merged.bin
$(ESPTOOL_BINS)
$(Q) echo nuttx.merged.bin >> nuttx.manifest
$(Q) echo "Generated: nuttx.merged.bin"
endef
@@ -106,7 +98,7 @@ endef
# MKIMAGE -- Convert an ELF file into a compatible binary file
define MKIMAGE
- $(Q) echo "MKIMAGE: ESP32-C3 binary"
+ $(Q) echo "MKIMAGE: NuttX binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install
esptool\""; \
@@ -115,12 +107,13 @@ define MKIMAGE
exit 1; \
fi
$(Q) if [ -z $(FLASH_SIZE) ]; then \
- echo "Missing Flash memory size configuration for the ESP32-C3
chip."; \
+ echo "Missing Flash memory size configuration."; \
exit 1; \
fi
- esptool.py -c $(CHIP_SERIES) elf2image $(ESPTOOL_FLASH_OPTS) -o
nuttx.bin nuttx
+ $(eval ELF2IMAGE_OPTS := -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff
$(FLASH_FREQ))
+ esptool.py -c $(CHIP_SERIES) elf2image $(ELF2IMAGE_OPTS) -o nuttx.bin
nuttx
$(Q) echo nuttx.bin >> nuttx.manifest
- $(Q) echo "Generated: nuttx.bin (ESP32-C3 compatible)"
+ $(Q) echo "Generated: nuttx.bin"
endef
# POSTBUILD -- Perform post build operations
@@ -144,5 +137,6 @@ define FLASH
fi
$(eval ESPTOOL_OPTS := -c $(CHIP_SERIES) -p $(ESPTOOL_PORT) -b
$(ESPTOOL_BAUD) $(if $(CONFIG_ESPRESSIF_ESPTOOLPY_NO_STUB),--no-stub))
- esptool.py $(ESPTOOL_OPTS) write_flash $(ESPTOOL_WRITEFLASH_OPTS)
$(ESPTOOL_BINS)
+ $(eval WRITEFLASH_OPTS := $(if $(CONFIG_ESPRESSIF_MERGE_BINS),0x0
nuttx.merged.bin,$(if $(CONFIG_ESPRESSIF_FLASH_DETECT),-fs detect) -fm dio
$(ESPTOOL_BINS)))
+ esptool.py $(ESPTOOL_OPTS) write_flash $(WRITEFLASH_OPTS)
endef
