TimJTi commented on code in PR #7894: URL: https://github.com/apache/nuttx/pull/7894#discussion_r1050607397
########## arch/arm/src/sama5/sam_flexcom_spi.c: ########## @@ -0,0 +1,2116 @@ +/**************************************************************************** + * arch/arm/src/sama5/sam_flexcom_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <inttypes.h> +#include <stdint.h> +#include <stdbool.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include <assert.h> +#include <debug.h> + +#include <arch/board/board.h> + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <nuttx/kmalloc.h> +#include <nuttx/wdog.h> +#include <nuttx/clock.h> +#include <nuttx/mutex.h> +#include <nuttx/spi/spi.h> + +#include "arm_internal.h" + +#include "chip.h" +#include "sam_pio.h" +#include "sam_dmac.h" +#include "sam_memories.h" +#include "sam_periphclks.h" +#include "sam_flexcom_spi.h" +#include "hardware/sam_pmc.h" +#include "hardware/sam_flexcom_spi.h" +#include "hardware/sam_flexcom.h" +#include "hardware/sam_pinmap.h" + +#if defined(CONFIG_SAMA5_FLEXCOM0_SPI) || \ + defined(CONFIG_SAMA5_FLEXCOM1_SPI) || \ + defined(CONFIG_SAMA5_FLEXCOM2_SPI) || \ + defined(CONFIG_SAMA5_FLEXCOM3_SPI) || \ + defined(CONFIG_SAMA5_FLEXCOM4_SPI) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* When SPI DMA is enabled, small DMA transfers will still be performed by + * polling logic. But we need a threshold value to determine what is small. + * That value is provided by CONFIG_SAMA5_SPI_DMATHRESHOLD. + */ + +# ifndef CONFIG_SAMA5_SPI_DMATHRESHOLD +# define CONFIG_SAMA5_SPI_DMATHRESHOLD 4 +# endif + +# ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMA5_SPI_REGDEBUG +# endif + +# ifdef CONFIG_SAMA5_SPI_DMA + +# if defined(CONFIG_SAMA5_FLEXCOM0_SPI) && defined(CONFIG_SAMA5_XDMAC0) +# define SAMA5_FLEXCOM0_SPI_DMA true +# else +# define SAMA5_FLEXCOM0_SPI_DMA false +# endif + +# if defined(CONFIG_SAMA5_FLEXCOM1_SPI) && defined(CONFIG_SAMA5_XDMAC0) +# define SAMA5_FLEXCOM1_SPI_DMA true +# else +# define SAMA5_FLEXCOM1_SPI_DMA false +# endif + +# if defined(CONFIG_SAMA5_FLEXCOM1_SPI) && defined(CONFIG_SAMA5_XDMAC0) +# define SAMA5_FLEXCOM2_SPI_DMA true +# else +# define SAMA5_FLEXCOM2_SPI_DMA false +# endif + +# if defined(CONFIG_SAMA5_FLEXCOM3_SPI) && defined(CONFIG_SAMA5_XDMAC0) +# define SAMA5_FLEXCOM3_SPI_DMA true +# else +# define SAMA5_FLEXCOM3_SPI_DMA false +# endif + +# if defined(CONFIG_SAMA5_FLEXCOM4_SPI) && defined(CONFIG_SAMA5_XDMAC0) +# define SAMA5_FLEXCOM4_SPI_DMA true +# else +# define SAMA5_FLEXCOM4_SPI_DMA false +# endif + +#endif + +#ifndef CONFIG_SAMA5_SPI_DMA +# undef CONFIG_SAMA5_SPI_DMADEBUG +#endif + +/* Clocking *****************************************************************/ + +/* Select MCU-specific settings + * + * SPI is driven by the main clock. + */ + +#define SAM_FLEXCOM_SPI_CLOCK BOARD_MCK_FREQUENCY + +/* DMA timeout. The value is not critical; we just don't want the system to + * hang in the event that a DMA does not finish. This is set to + */ + +#define DMA_TIMEOUT_MS (800) +#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS) + +/* Debug ********************************************************************/ + +/* Check if SPI debug is enabled */ + +#ifndef CONFIG_DEBUG_DMA +# undef CONFIG_SAMA5_SPI_DMADEBUG +#endif + +#define DMA_INITIAL 0 +#define DMA_AFTER_SETUP 1 +#define DMA_AFTER_START 2 +#define DMA_CALLBACK 3 +#define DMA_TIMEOUT 3 +#define DMA_END_TRANSFER 4 +#define DMA_NSAMPLES 5 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The state of the one SPI chip select */ + +struct sam_flex_spics_s +{ + struct spi_dev_s flex_spidev; /* Externally visible part of the + * SPI interface */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t nbits; /* Width of word in bits (8 to 16) */ + uint8_t mode; /* Mode 0,1,2,3 */ + +#if defined(CONFIG_SAMA5_FLEXCOM0_SPI) || \ + defined(CONFIG_SAMA5_FLEXCOM1_SPI) || \ + defined(CONFIG_SAMA5_FLEXCOM2_SPI) || \ + defined(CONFIG_SAMA5_FLEXCOM3_SPI) || \ + defined(CONFIG_SAMA5_FLEXCOM4_SPI) + uint8_t flex_spino; /* SPI controller number (0 or 1) */ +#endif + uint8_t cs; /* Chip select number */ + +#ifdef CONFIG_SAMA5_SPI_DMA + bool candma; /* DMA is supported */ + sem_t dmawait; /* Used to wait for DMA completion */ + struct wdog_s dmadog; /* Watchdog that handles DMA timeouts */ + int result; /* DMA result */ + DMA_HANDLE rxdma; /* SPI RX DMA handle */ + DMA_HANDLE txdma; /* SPI TX DMA handle */ +#endif + + /* Debug stuff */ + +#ifdef CONFIG_SAMA5_SPI_DMADEBUG + struct sam_dmaregs_s rxdmaregs[DMA_NSAMPLES]; + struct sam_dmaregs_s txdmaregs[DMA_NSAMPLES]; +#endif +}; + +/* Type of board-specific SPI status function */ + +typedef void (*select_t)(uint32_t devid, bool selected); + +/* Chip select register offsetrs */ + +/* The overall state of one SPI controller */ + +struct sam_flex_spidev_s +{ + uint32_t base; /* SPI controller register base address */ + mutex_t spilock; /* Assures mutually exclusive access to SPI */ + select_t select; /* SPI select callout */ + bool initialized; /* TRUE: Controller has been initialized */ +#ifdef CONFIG_SAMA5_SPI_DMA + uint8_t pid; /* Peripheral ID */ +#endif + + /* Debug stuff */ + +#ifdef CONFIG_SAMA5_SPI_REGDEBUG + bool wrlast; /* Last was a write */ + uint32_t addresslast; /* Last address */ + uint32_t valuelast; /* Last value */ + int ntimes; /* Number of times */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +#ifdef CONFIG_SAMA5_SPI_REGDEBUG +static bool flex_spi_checkreg(struct sam_flex_spidev_s *flex_spi, + bool wr, uint32_t value, uint32_t address); +#else +# define flex_spi_checkreg(flex_spi,wr,value,address) (false) +#endif + +static inline uint32_t flex_spi_getreg(struct sam_flex_spidev_s *flex_spi, + unsigned int offset); +static inline void flex_spi_putreg(struct sam_flex_spidev_s *spi, + uint32_t value, unsigned int offset); +static inline struct sam_flex_spidev_s + *flex_spi_dev(struct sam_flex_spics_s *flex_spics); + +#ifdef CONFIG_DEBUG_SPI_INFO +static void flex_spi_dumpregs(struct sam_flex_spidev_s *flex_spi, + const char *msg); +#else +# define flex_spi_dumpregs(flex_spi,msg) +#endif + +static inline void flex_spi_flush(struct sam_flex_spidev_s *flex_spi); +static inline uint32_t flex_spi_cs2pcs(struct sam_flex_spics_s *flex_spics); + +/* DMA support */ + +#ifdef CONFIG_SAMA5_SPI_DMA + +# ifdef CONFIG_SAMA5_SPI_DMADEBUG +# define spi_rxdma_sample(s,i) sam_dmasample((s)->rxdma, &(s)->rxdmaregs[i]) +# define spi_txdma_sample(s,i) sam_dmasample((s)->txdma, &(s)->txdmaregs[i]) +static void flex_spi_dma_sampleinit(struct sam_flex_spics_s *flex_spics); +static void flex_spi_dma_sampledone(struct sam_flex_spics_s *flex_spics); + +# else +# define flex_spi_rxdma_sample(s,i) +# define flex_spi_txdma_sample(s,i) +# define flex_spi_dma_sampleinit(s) +# define flex_spi_dma_sampledone(s) + +# endif + +static void flex_spi_rxcallback(DMA_HANDLE handle, void *arg, int result); +static void flex_spi_txcallback(DMA_HANDLE handle, void *arg, int result); +static inline uintptr_t flex_spi_physregaddr( + struct sam_flex_spics_s *flex_spics, + unsigned int offset); +#endif + +/* SPI methods */ + +static int flex_spi_lock(struct spi_dev_s *dev, bool lock); +static void flex_spi_select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +static uint32_t flex_spi_setfrequency(struct spi_dev_s *dev, uint32_t freq); +static void flex_spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode); +static void flex_spi_setbits(struct spi_dev_s *dev, int nbits); +static uint32_t flex_spi_send(struct spi_dev_s *dev, uint32_t wd); + +#ifdef CONFIG_SAMA5_SPI_DMA +static void flex_spi_exchange_nodma(struct spi_dev_s *dev, + const void *txbuffer, void *rxbuffer, + size_t nwords); +#endif +static void flex_spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void flex_spi_sndblock(struct spi_dev_s *dev, + const void *buffer, size_t nwords); +static void flex_spi_recvblock(struct spi_dev_s *dev, void *buffer, + size_t nwords); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps chip select numbers (0-1) to CSR register offsets */ + +static const uint16_t g_csroffset[2] = +{ + SAM_FLEXCOM_SPI_CSR0_OFFSET, SAM_FLEXCOM_SPI_CSR1_OFFSET +}; + +#ifdef CONFIG_SAMA5_FLEXCOM0_SPI +/* FLEXCOM0 SPI driver operations */ + +static const struct spi_ops_s g_flexcom0_spiops = +{ + .lock = flex_spi_lock, + .select = flex_spi_select, + .setfrequency = flex_spi_setfrequency, + .setmode = flex_spi_setmode, + .setbits = flex_spi_setbits, +# ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = 0, /* Not supported */ +# endif + .status = sam_flexcom0_spistatus, +# ifdef CONFIG_SPI_CMDDATA + .cmddata = sam_flexcom0_spicmddata, +# endif + .send = flex_spi_send, +# ifdef CONFIG_SPI_EXCHANGE + .exchange = flex_spi_exchange, +# else + .sndblock = flex_spi_sndblock, + .recvblock = flex_spi_recvblock, +# endif + .registercallback = 0, /* Not implemented */ +}; + +/* This is the overall state of the FLEXCOM0 SPI controller */ + +static struct sam_flex_spidev_s g_flexcom0dev = +{ + .base = SAM_FLEXCOM0_VBASE, + .spilock = NXMUTEX_INITIALIZER, + .select = sam_flexcom0_spiselect, +# ifdef SAMA5_FLEXCOM0_SPI_DMA + .pid = SAM_PID_FLEXCOM0, +# endif +}; +#endif /* CONFIG_SAMA5_FLEXCOM0_SPI */ + +#ifdef CONFIG_SAMA5_FLEXCOM1_SPI +/* FLEXCOM1 SPI driver operations */ + +static const struct spi_ops_s g_flexcom1_spiops = +{ + .lock = flex_spi_lock, + .select = flex_spi_select, + .setfrequency = flex_spi_setfrequency, + .setmode = flex_spi_setmode, + .setbits = flex_spi_setbits, +# ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = 0, /* Not supported */ +# endif + .status = sam_flexcom1_spistatus, +# ifdef CONFIG_SPI_CMDDATA + .cmddata = sam_flexcom1_spicmddata, +# endif + .send = flex_spi_send, +# ifdef CONFIG_SPI_EXCHANGE + .exchange = flex_spi_exchange, +# else + .sndblock = flex_spi_sndblock, + .recvblock = flex_spi_recvblock, +# endif + .registercallback = 0, /* Not implemented */ +}; + +/* This is the overall state of the FLEXCOM1 SPI controller */ + +static struct sam_flex_spidev_s g_flexcom1dev = +{ + .base = SAM_FLEXCOM1_VBASE, + .spilock = NXMUTEX_INITIALIZER, + .select = sam_flexcom1_spiselect, +# ifdef SAMA5_FLEXCOM1_SPI_DMA + .pid = SAM_PID_FLEXCOM1, +# endif +}; +#endif /* CONFIG_SAMA5_FLEXCOM1_SPI */ + +#ifdef CONFIG_SAMA5_FLEXCOM2_SPI +/* FLEXCOM2 SPI driver operations */ + +static const struct spi_ops_s g_flexcom2_spiops = +{ + .lock = flex_spi_lock, + .select = flex_spi_select, + .setfrequency = flex_spi_setfrequency, + .setmode = flex_spi_setmode, + .setbits = flex_spi_setbits, +# ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = 0, /* Not supported */ +# endif + .status = sam_flexcom2_spistatus, +# ifdef CONFIG_SPI_CMDDATA + .cmddata = sam_flexcom2_spicmddata, +# endif + .send = flex_spi_send, +# ifdef CONFIG_SPI_EXCHANGE + .exchange = flex_spi_exchange, +# else + .sndblock = flex_spi_sndblock, + .recvblock = flex_spi_recvblock, +# endif + .registercallback = 0, /* Not implemented */ +}; + +/* This is the overall state of the FLEXCOM2 SPI controller */ + +static struct sam_flex_spidev_s g_flexcom2dev = +{ + .base = SAM_FLEXCOM2_VBASE, + .spilock = NXMUTEX_INITIALIZER, + .select = sam_flexcom2_spiselect, +# ifdef SAMA5_FLEXCOM2_SPI_DMA + .pid = SAM_PID_FLEXCOM2, +# endif +}; +#endif /* CONFIG_SAMA5_FLEXCOM2_SPI */ + +#ifdef CONFIG_SAMA5_FLEXCOM3_SPI +/* FLEXCOM3 SPI driver operations */ + +static const struct spi_ops_s g_flexcom3_spiops = +{ + .lock = flex_spi_lock, + .select = flex_spi_select, + .setfrequency = flex_spi_setfrequency, + .setmode = flex_spi_setmode, + .setbits = flex_spi_setbits, +# ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = 0, /* Not supported */ +# endif + .status = sam_flexcom3_spistatus, +# ifdef CONFIG_SPI_CMDDATA + .cmddata = sam_flexcom3_spicmddata, +# endif + .send = flex_spi_send, +# ifdef CONFIG_SPI_EXCHANGE + .exchange = flex_spi_exchange, +# else + .sndblock = flex_spi_sndblock, + .recvblock = flex_spi_recvblock, +# endif + .registercallback = 0, /* Not implemented */ +}; + +/* This is the overall state of the FLEXCOM3 SPI controller */ + +static struct sam_flex_spidev_s g_flexcom3dev = +{ + .base = SAM_FLEXCOM3_VBASE, + .spilock = NXMUTEX_INITIALIZER, + .select = sam_flexcom3_spiselect, +# ifdef SAMA5_FLEXCOM3_SPI_DMA + .pid = SAM_PID_FLEXCOM3, +# endif +}; +#endif /* CONFIG_SAMA5_FLEXCOM3_SPI */ + +#ifdef CONFIG_SAMA5_FLEXCOM4_SPI +/* FLEXCOM4 SPI driver operations */ + +static const struct spi_ops_s g_flexcom4_spiops = +{ + .lock = flex_spi_lock, + .select = flex_spi_select, + .setfrequency = flex_spi_setfrequency, + .setmode = flex_spi_setmode, + .setbits = flex_spi_setbits, +# ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = 0, /* Not supported */ +# endif + .status = sam_flexcom4_spistatus, +# ifdef CONFIG_SPI_CMDDATA + .cmddata = sam_flexcom4_spicmddata, +# endif + .send = flex_spi_send, +# ifdef CONFIG_SPI_EXCHANGE + .exchange = flex_spi_exchange, +# else + .sndblock = flex_spi_sndblock, + .recvblock = flex_spi_recvblock, +# endif + .registercallback = 0, /* Not implemented */ +}; + +/* This is the overall state of the FLEXCOM4 SPI controller */ + +static struct sam_flex_spidev_s g_flexcom4dev = +{ + .base = SAM_FLEXCOM4_VBASE, + .spilock = NXMUTEX_INITIALIZER, + .select = sam_flexcom4_spiselect, +# ifdef SAMA5_FLEXCOM4_SPI_DMA + .pid = SAM_PID_FLEXCOM4, +# endif +}; +#endif /* CONFIG_SAMA5_FLEXCOM4_SPI */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: flex_spi_checkreg + * + * Description: + * Check if the current register access is a duplicate of the preceding. + * + * Input Parameters: + * value - The value to be written + * address - The address of the register to write to + * + * Returned Value: + * true: This is the first register access of this type. + * flase: This is the same as the preceding register access. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMA5_SPI_REGDEBUG +static bool flex_spi_checkreg(struct sam_flex_spidev_s *flex_spi, bool wr, + uint32_t value, uint32_t address) +{ + if (wr == flex_spi->wrlast && /* Same kind of access? */ + value == flex_spi->valuelast && /* Same value? */ + address == flex_spi->addresslast) /* Same address? */ + { + /* Yes, then just keep a count of the number of times we did this. */ + + flex_spi->ntimes++; + return false; + } + else + { + /* Did we do the previous operation more than once? */ + + if (flex_spi->ntimes > 0) + { + /* Yes... show how many times we did it */ + + spiinfo("...[Repeats %d times]...\n", flex_spi->ntimes); + } + + /* Save information about the new access */ + + flex_spi->wrlast = wr; + flex_spi->valuelast = value; + flex_spi->addresslast = address; + flex_spi->ntimes = 0; + } + + /* Return true if this is the first time that we have done this operation */ + + return true; +} +#endif /* CONFIG_SAMA5_SPI_REGDEBUG */ + +/**************************************************************************** + * Name: flex_spi_getreg + * + * Description: + * Read an SPI register + * + ****************************************************************************/ + +static inline uint32_t flex_spi_getreg(struct sam_flex_spidev_s *flex_spi, + unsigned int offset) +{ + uint32_t address = flex_spi->base + offset; + uint32_t value = getreg32(address); + +#ifdef CONFIG_SAMA5_SPI_REGDEBUG + if (flex_spi_checkreg(flex_spi, false, value, address)) + { + spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); + } +#endif + + return value; +} + +/**************************************************************************** + * Name: flex_spi_putreg + * + * Description: + * Write a value to an SPI register + * + ****************************************************************************/ + +static inline void flex_spi_putreg(struct sam_flex_spidev_s *flex_spi, + uint32_t value, unsigned int offset) +{ + uint32_t address = flex_spi->base + offset; + +#ifdef CONFIG_SAMA5_SPI_REGDEBUG + if (flex_spi_checkreg(flex_spi, true, value, address)) + { + spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); + } +#endif + + putreg32(value, address); +} + +/**************************************************************************** + * Name: flex_spi_dumpregs + * + * Description: + * Dump the contents of all SPI registers + * + * Input Parameters: + * spi - The SPI controller to dump + * msg - Message to print before the register data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_SPI_INFO +static void flex_spi_dumpregs(struct sam_flex_spidev_s *flex_spi, + const char *msg) +{ + spiinfo("%s:\n", msg); + spiinfo(" MR:%08x SR:%08x IMR:%08x\n", + getreg32(flex_spi->base + SAM_FLEXCOM_SPI_MR_OFFSET), + getreg32(flex_spi->base + SAM_FLEXCOM_SPI_SR_OFFSET), + getreg32(flex_spi->base + SAM_FLEXCOM_SPI_IMR_OFFSET)); + spiinfo(" CSR0:%08x CSR1:%08x \n", + getreg32(flex_spi->base + SAM_FLEXCOM_SPI_CSR0_OFFSET), + getreg32(flex_spi->base + SAM_FLEXCOM_SPI_CSR1_OFFSET)); + spiinfo(" WPCR:%08x WPSR:%08x\n", + getreg32(flex_spi->base + SAM_FLEXCOM_SPI_WPCR_OFFSET), + getreg32(flex_spi->base + SAM_FLEXCOM_SPI_WPSR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: flex_spi_dev + * + * Description: + * Given a chip select instance, return a pointer to the parent SPI + * controller instance. + * + ****************************************************************************/ + +static inline struct sam_flex_spidev_s *flex_spi_dev(struct sam_flex_spics_s + *flex_spics) +{ +#ifdef CONFIG_SAMA5_FLEXCOM0_SPI + if (flex_spics->flex_spino == 0) + return &g_flexcom0dev; +#endif +#ifdef CONFIG_SAMA5_FLEXCOM1_SPI + if (flex_spics->flex_spino == 1) + return &g_flexcom1dev; +#endif +#ifdef CONFIG_SAMA5_FLEXCOM2_SPI + if (flex_spics->flex_spino == 2) + return &g_flexcom2dev; +#endif +#ifdef CONFIG_SAMA5_FLEXCOM3_SPI + if (flex_spics->flex_spino == 3) + return &g_flexcom3dev; +#endif +#ifdef CONFIG_SAMA5_FLEXCOM4_SPI + if (flex_spics->flex_spino == 4) + return &g_flexcom4dev; +#endif Review Comment: I followed the method in sam_spi.c (which is just for SPI0 and SPI1), and changed/extended it. We need to make sure the test isn't done for any interfaces not actually in use, but I'll check to see if we would ever get to this code if not and revise as appropriate. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
