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The following commit(s) were added to refs/heads/master by this push: new 4b6c9915fe arch: qemu-rv: Fix timer and IPI handling for BUILD_KERNEL+SMP 4b6c9915fe is described below commit 4b6c9915fe33685367dc7e3fef707e3378fc7cee Author: Masayuki Ishikawa <masayuki.ishik...@gmail.com> AuthorDate: Sat Oct 8 15:51:12 2022 +0900 arch: qemu-rv: Fix timer and IPI handling for BUILD_KERNEL+SMP Summary: - I noticed that the OS timer sometimes proceeds fast when a task is scheduled to run on CPUO via IPI. - Actually, qemu-rv implementation shares supervisor software interrupt for both timer and IPI on CPU0. - This commit fixes this issue. Impact: - qemu-rv only Testing: - Tested with qemu-6.2 Signed-off-by: Masayuki Ishikawa <masayuki.ishik...@jp.sony.com> --- arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c | 32 ++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c b/arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c index 2e8e0a6f61..1492de5a3b 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c @@ -48,11 +48,18 @@ #define MTIMER_FREQ 10000000 #define TICK_COUNT (10000000 / TICK_PER_SEC) +#ifdef CONFIG_BUILD_KERNEL + /**************************************************************************** - * Private Functions + * Private Data ****************************************************************************/ -#ifdef CONFIG_BUILD_KERNEL +static uint32_t g_mtimer_cnt = 0; +static uint32_t g_stimer_pending = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ /**************************************************************************** * Name: qemu_rv_ssoft_interrupt @@ -69,9 +76,23 @@ static int qemu_rv_ssoft_interrupt(int irq, void *context, void *arg) CLEAR_CSR(sip, SIP_SSIP); - /* Proceed the OS timer */ + if (g_stimer_pending) + { + g_stimer_pending = false; + + /* Proceed the OS timer */ + + nxsched_process_timer(); + } +#ifdef CONFIG_SMP + else + { + /* We assume IPI has been issued */ + + riscv_pause_handler(irq, context, arg); + } +#endif - nxsched_process_timer(); return 0; } @@ -174,6 +195,9 @@ void qemu_rv_mtimer_interrupt(void) next = current + TICK_COUNT; putreg64(next, QEMU_RV_CLINT_MTIMECMP); + g_mtimer_cnt++; + g_stimer_pending = true; + /* Post Supervisor Software Interrupt */ SET_CSR(sip, SIP_SSIP);