hartmannathan commented on code in PR #6478: URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r918046448
########## arch/arm64/src/common/arm64_mmu.c: ########## @@ -0,0 +1,618 @@ +/*************************************************************************** + * arch/arm64/src/common/arm64_mmu.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> +#include <debug.h> +#include <assert.h> + +#include <nuttx/arch.h> +#include <arch/irq.h> +#include <arch/chip/chip.h> + +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "arm64_fatal.h" +#include "arm64_mmu.h" + +/*************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* MMU debug option + * #define CONFIG_MMU_ASSERT 1 + * #define CONFIG_MMU_DEBUG 1 + * #define CONFIG_MMU_DUMP_PTE 1 + */ + +#ifdef CONFIG_MMU_DEBUG + +#define L0_SPACE "" +#define L1_SPACE " " +#define L2_SPACE " " +#define L3_SPACE " " +#define XLAT_TABLE_LEVEL_SPACE(level) \ + (((level) == 0) ? L0_SPACE : \ + ((level) == 1) ? L1_SPACE : \ + ((level) == 2) ? L2_SPACE : L3_SPACE) +#endif + +#ifdef CONFIG_MMU_ASSERT +#define __MMU_ASSERT(__cond, fmt, ...) \ + do { \ + if (!(__cond)){ \ + trace_printf(fmt, ## __VA_ARGS__); \ + PANIC(); \ + } \ + } while (false) +#else +#define __MMU_ASSERT(test, fmt, ...) +#endif + +/* We support only 4kB translation granule */ + +#define PAGE_SIZE_SHIFT 12U +#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT) +#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one + * complete table */ +#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT) + +#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */ +#define XLAT_TABLE_LEVEL_MAX 3U + +#define XLAT_TABLE_ENTRIES_SHIFT \ + (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT) +#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT) + +/* Address size covered by each entry at given translation table level */ + +#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT +#define L2_XLAT_VA_SIZE_SHIFT \ + (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L1_XLAT_VA_SIZE_SHIFT \ + (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L0_XLAT_VA_SIZE_SHIFT \ + (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) + +#define LEVEL_TO_VA_SIZE_SHIFT(level) \ + (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \ + (XLAT_TABLE_LEVEL_MAX - (level)))) + +/* Virtual Address Index within given translation table level */ + +#define XLAT_TABLE_VA_IDX(va_addr, level) \ + ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1)) + +/* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS + * For a 4 KB page size, + * (va_bits <= 21) - base level 3 + * (22 <= va_bits <= 30) - base level 2 + * (31 <= va_bits <= 39) - base level 1 + * (40 <= va_bits <= 48) - base level 0 + */ + +#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \ + ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \ + ? 0U \ + : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \ + ? 1U \ + : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \ + ? 2U : 3U) + +#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS) + +#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \ + (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL))) + +#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \ + CONFIG_ARM64_VA_BITS) + +static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data( + NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)); + +static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] +aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t)); + +#if (CONFIG_ARM64_PA_BITS == 48) +#define TCR_PS_BITS TCR_PS_BITS_256TB +#elif (CONFIG_ARM64_PA_BITS == 44) +#define TCR_PS_BITS TCR_PS_BITS_16TB +#elif (CONFIG_ARM64_PA_BITS == 42) +#define TCR_PS_BITS TCR_PS_BITS_4TB +#elif (CONFIG_ARM64_PA_BITS == 40) +#define TCR_PS_BITS TCR_PS_BITS_1TB +#elif (CONFIG_ARM64_PA_BITS == 36) +#define TCR_PS_BITS TCR_PS_BITS_64GB +#else +#define TCR_PS_BITS TCR_PS_BITS_4GB +#endif + +/*************************************************************************** + * Private Data + ***************************************************************************/ + +/* NuttX RTOS execution regions with appropriate attributes */ + +static const struct arm_mmu_region mmu_nxrt_regions[] = +{ + /* Mark text segment cacheable,read only and executable */ + + MMU_REGION_FLAT_ENTRY("nx_code", + (uint64_t)_stext, + (uint64_t)_sztext, + MT_CODE | MT_SECURE), + + /* Mark rodata segment cacheable, read only and execute-never */ + + MMU_REGION_FLAT_ENTRY("nx_rodata", + (uint64_t)_srodata, + (uint64_t)_szrodata, + MT_RODATA | MT_SECURE), + + /* Mark rest of the mirtos execution regions (data, bss, noinit, etc.) + * cacheable, read-write + * Note: read-write region is marked execute-ever internally + */ + + MMU_REGION_FLAT_ENTRY("nx_data", + (uint64_t)_sdata, + (uint64_t)_szdata, + MT_NORMAL | MT_RW | MT_SECURE), +}; + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +/* Translation table control register settings */ + +static uint64_t get_tcr(int el) +{ + uint64_t tcr; + uint64_t va_bits = CONFIG_ARM64_VA_BITS; + uint64_t tcr_ps_bits; + + tcr_ps_bits = TCR_PS_BITS; + + if (el == 1) + { + tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT); + + /* TCR_EL1.EPD1: Disable translation table walk for addresses + * that are translated using TTBR1_EL1. + */ + + tcr |= TCR_EPD1_DISABLE; + } + else + { + tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT); + } + + tcr |= TCR_T0SZ(va_bits); + + /* Translation table walk is cacheable, inner/outer WBWA and + * inner shareable + */ + + tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA; + + return tcr; +} + +static int pte_desc_type(uint64_t *pte) +{ + return *pte & PTE_DESC_TYPE_MASK; +} + +static uint64_t *calculate_pte_index(uint64_t addr, int level) +{ + int base_level = XLAT_TABLE_BASE_LEVEL; + uint64_t *pte; + uint64_t idx; + unsigned int i; + + /* Walk through all translation tables to find pte index */ + + pte = (uint64_t *)base_xlat_table; + for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++) + { + idx = XLAT_TABLE_VA_IDX(addr, i); + pte += idx; + + /* Found pte index */ + + if (i == level) + { + return pte; + } + + /* if PTE is not table desc, can't traverse */ + + if (pte_desc_type(pte) != PTE_TABLE_DESC) + { + return NULL; + } + + /* Move to the next translation table level */ + + pte = (uint64_t *)(*pte & 0x0000fffffffff000); + } + + return NULL; +} + +static void set_pte_table_desc(uint64_t *pte, uint64_t *table, + unsigned int level) +{ +#ifdef CONFIG_MMU_DEBUG + sinfo("%s", XLAT_TABLE_LEVEL_SPACE(level)); + sinfo("%p: [Table] %p\n", pte, table); +#endif + + /* Point pte to new table */ + + *pte = PTE_TABLE_DESC | (uint64_t)table; +} + +static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa, + unsigned int attrs, unsigned int level) +{ + uint64_t desc = addr_pa; + unsigned int mem_type; + + desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC; + + /* NS bit for security memory access from secure state */ + + desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0; + + /* AP bits for Data access permission */ + + desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO; + + /* the access flag */ + + desc |= PTE_BLOCK_DESC_AF; + + /* memory attribute index field */ + + mem_type = MT_TYPE(attrs); + desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type); + + switch (mem_type) + { + case MT_DEVICE_NGNRNE: + case MT_DEVICE_NGNRE: + case MT_DEVICE_GRE: + { + /* Access to Device memory and non-cacheable memory are coherent + * for all observers in the system and are treated as + * Outer shareable, so, for these 2 types of memory, + * it is not strictly needed to set shareability field + */ + + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + + /* Map device memory as execute-never */ + + desc |= PTE_BLOCK_DESC_PXN; + desc |= PTE_BLOCK_DESC_UXN; + break; + } + + case MT_NORMAL_NC: + case MT_NORMAL: + { + /* Make Normal RW memory as execute never */ + + if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER)) + { + desc |= PTE_BLOCK_DESC_PXN; + } + + if (mem_type == MT_NORMAL) + { + desc |= PTE_BLOCK_DESC_INNER_SHARE; + } + else + { + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + } + } + } + +#if defined(CONFIG_MMU_DEBUG) && defined(CONFIG_MMU_DUMP_PTE) + sinfo("%s ", XLAT_TABLE_LEVEL_SPACE(level)); + sinfo("%p: ", pte); + sinfo("%s ", + (mem_type == + MT_NORMAL) ? "MEM" :((mem_type == MT_NORMAL_NC) ? "NC" : "DEV")); + sinfo("%s ", (attrs & MT_RW) ? "-RW" : "-RO"); + sinfo("%s ", (attrs & MT_NS) ? "-NS" : "-S"); + sinfo("%s ", (attrs & MT_EXECUTE_NEVER) ? "-XN" : "-EXEC"); + sinfo("\n"); +#endif + + *pte = desc; +} + +/* Returns a new reallocated table */ + +static uint64_t *new_prealloc_table(void) +{ + static unsigned int table_idx; + + __MMU_ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES, + "Enough xlat tables not allocated"); + + return (uint64_t *)(xlat_tables[table_idx++]); +} + +/* Splits a block into table with entries spanning the old block */ + +static void split_pte_block_desc(uint64_t *pte, int level) +{ + uint64_t old_block_desc = *pte; + uint64_t *new_table; + unsigned int i = 0; + + /* get address size shift bits for next level */ + + int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1); + +#ifdef CONFIG_MMU_DEBUG + sinfo("Splitting existing PTE %p(L%d)\n", pte, level); +#endif + + new_table = new_prealloc_table(); + + for (i = 0; i < XLAT_TABLE_ENTRIES; i++) + { + new_table[i] = old_block_desc | (i << levelshift); + + if ((level + 1) == 3) + { + new_table[i] |= PTE_PAGE_DESC; + } + } + + /* Overwrite existing PTE set the new table into effect */ + + set_pte_table_desc(pte, new_table, level); +} + +/* Create/Populate translation table(s) for given region */ + +static void init_xlat_tables(const struct arm_mmu_region *region) +{ + uint64_t *pte; + uint64_t virt = region->base_va; + uint64_t phys = region->base_pa; + uint64_t size = region->size; + uint64_t attrs = region->attrs; + uint64_t level_size; + uint64_t *new_table; + unsigned int level = XLAT_TABLE_BASE_LEVEL; + +#ifdef CONFIG_MMU_DEBUG + sinfo("mmap: virt %llx phys %llx size %llx\n", virt, phys, size); +#endif + + /* check minimum alignment requirement for given mmap region */ + + __MMU_ASSERT(((virt & (PAGE_SIZE - 1)) == 0) && + ((size & (PAGE_SIZE - 1)) == 0), + "address/size are not page aligned\n"); + + while (size) + { + __MMU_ASSERT(level <= XLAT_TABLE_LEVEL_MAX, + "max translation table level exceeded\n"); + + /* Locate PTE for given virtual address and page table level */ + + pte = calculate_pte_index(virt, level); + __MMU_ASSERT(pte != NULL, "pte not found\n"); + + level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level); + + if (size >= level_size && !(virt & (level_size - 1))) + { + /* Given range fits into level size, + * create block/page descriptor + */ + + set_pte_block_desc(pte, phys, attrs, level); + virt += level_size; + phys += level_size; + size -= level_size; + + /* Range is mapped, start again for next range */ + + level = XLAT_TABLE_BASE_LEVEL; + } + else if (pte_desc_type(pte) == PTE_INVALID_DESC) + { + /* Range doesn't fit, create subtable */ + + new_table = new_prealloc_table(); + set_pte_table_desc(pte, new_table, level); + level++; + } + else if (pte_desc_type(pte) == PTE_BLOCK_DESC) + { + split_pte_block_desc(pte, level); + level++; + } + else if (pte_desc_type(pte) == PTE_TABLE_DESC) + { + level++; + } + } +} + +static void setup_page_tables(void) +{ + unsigned int index; + const struct arm_mmu_region *region; + uint64_t max_va = 0, max_pa = 0; + + for (index = 0; index < mmu_config.num_regions; index++) + { + region = &mmu_config.mmu_regions[index]; + max_va = MAX(max_va, region->base_va + region->size); + max_pa = MAX(max_pa, region->base_pa + region->size); + } + + __MMU_ASSERT(max_va <= (1ULL << CONFIG_ARM64_VA_BITS), + "Maximum VA not supported\n"); + __MMU_ASSERT(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS), + "Maximum PA not supported\n"); + + /* create translation tables for user provided platform regions */ + + for (index = 0; index < mmu_config.num_regions; index++) + { + region = &mmu_config.mmu_regions[index]; + if (region->size || region->attrs) + { + init_xlat_tables(region); + } + } + + /* setup translation table for mirtos execution regions */ + + for (index = 0; index < ARRAY_SIZE(mmu_nxrt_regions); index++) + { + region = &mmu_nxrt_regions[index]; + if (region->size || region->attrs) + { + init_xlat_tables(region); + } + } +} + +static void enable_mmu_el1(unsigned int flags) +{ + uint64_t value; + Review Comment: Maybe add: `UNUSED(flags); ` ########## arch/arm64/src/qemu/qemu_serial.c: ########## @@ -0,0 +1,873 @@ +/*************************************************************************** + * arch/arm64/src/qemu/qemu_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include <nuttx/config.h> +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <unistd.h> +#include <string.h> +#include <assert.h> +#include <errno.h> +#include <debug.h> + +#ifdef CONFIG_SERIAL_TERMIOS +# include <termios.h> +#endif + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <nuttx/spinlock.h> +#include <nuttx/init.h> +#include <nuttx/fs/ioctl.h> +#include <nuttx/semaphore.h> +#include <nuttx/serial/serial.h> + +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "qemu_serial.h" +#include "arm64_arch_timer.h" +#include "qemu_boot.h" +#include "arm64_gic.h" + +#ifdef USE_SERIALDRIVER + +/*************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Which UART with be tty0/console and which tty1-4? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered UART. + */ + +/* First pick the console and ttys0. This could be any of UART1-5 */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#endif + +#define PL011_BIT_MASK(x, y) (((2 << (x)) - 1) << (y)) + +/* PL011 Uart Flags Register */ +#define PL011_FR_CTS BIT(0) /* clear to send - inverted */ +#define PL011_FR_DSR BIT(1) /* data set ready - inverted + */ +#define PL011_FR_DCD BIT(2) /* data carrier detect - + * inverted */ +#define PL011_FR_BUSY BIT(3) /* busy transmitting data */ +#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */ +#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */ +#define PL011_FR_RXFF BIT(6) /* receive FIFO full */ +#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */ +#define PL011_FR_RI BIT(8) /* ring indicator - inverted */ + +/* PL011 Integer baud rate register */ +#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */ + +/* PL011 Fractional baud rate register */ +#define PL011_FBRD_BAUD_DIVFRAC 0x3f +#define PL011_FBRD_WIDTH 6u + +/* PL011 Receive status register / error clear register */ +#define PL011_RSR_ECR_FE BIT(0) /* framing error */ +#define PL011_RSR_ECR_PE BIT(1) /* parity error */ +#define PL011_RSR_ECR_BE BIT(2) /* break error */ +#define PL011_RSR_ECR_OE BIT(3) /* overrun error */ + +#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \ + PL011_RSR_ECR_BE | PL011_RSR_ECR_OE) + +/* PL011 Line Control Register */ +#define PL011_LCRH_BRK BIT(0) /* send break */ +#define PL011_LCRH_PEN BIT(1) /* enable parity */ +#define PL011_LCRH_EPS BIT(2) /* select even parity */ +#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */ +#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */ +#define PL011_LCRH_WLEN_SHIFT 5 /* word length */ +#define PL011_LCRH_WLEN_WIDTH 2 +#define PL011_LCRH_SPS BIT(7) /* stick parity bit */ + +#define PL011_LCRH_WLEN_SIZE(x) ((x) - 5) + +#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \ + PL011_LCRH_SPS | \ + PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \ + PL011_LCRH_WLEN_SHIFT)) + +#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS) +#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN) +#define PL011_LCRH_PARITY_NONE (0) + +/* PL011 Control Register */ +#define PL011_CR_UARTEN BIT(0) /* enable uart operations */ +#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */ +#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */ +#define PL011_CR_LBE BIT(7) /* loop back enable */ +#define PL011_CR_TXE BIT(8) /* transmit enable */ +#define PL011_CR_RXE BIT(9) /* receive enable */ +#define PL011_CR_DTR BIT(10) /* data transmit ready */ +#define PL011_CR_RTS BIT(11) /* request to send */ +#define PL011_CR_Out1 BIT(12) +#define PL011_CR_Out2 BIT(13) +#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable + */ +#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable + */ + +/* PL011 Interrupt Fifo Level Select Register */ +#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */ +#define PL011_IFLS_TXIFLSEL_WIDTH 3 +#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */ +#define PL011_IFLS_RXIFLSEL_WIDTH 3 + +/* PL011 Interrupt Mask Set/Clear Register */ +#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */ +#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */ +#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */ +#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */ +#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */ +#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */ +#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt + * mask */ +#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt + * mask */ +#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask + */ +#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask + */ +#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt + * mask */ + +#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \ + PL011_IMSC_PEIM | PL011_IMSC_BEIM | \ + PL011_IMSC_OEIM) + +#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \ + PL011_IMSC_PEIM | PL011_IMSC_FEIM | \ + PL011_IMSC_RIMIM | \ + PL011_IMSC_CTSMIM | \ + PL011_IMSC_DCDMIM | \ + PL011_IMSC_DSRMIM | \ + PL011_IMSC_RXIM | PL011_IMSC_TXIM | \ + PL011_IMSC_RTIM) + +/*************************************************************************** + * Private Types + ***************************************************************************/ + +/* UART PL011 register map structure */ + +struct pl011_regs +{ + uint32_t dr; /* data register */ + union + { + uint32_t rsr; + uint32_t ecr; + }; + + uint32_t reserved_0[4]; + uint32_t fr; /* flags register */ + uint32_t reserved_1; + uint32_t ilpr; + uint32_t ibrd; + uint32_t fbrd; + uint32_t lcr_h; + uint32_t cr; + uint32_t ifls; + uint32_t imsc; + uint32_t ris; + uint32_t mis; + uint32_t icr; + uint32_t dmacr; +}; + +struct pl011_config +{ + volatile struct pl011_regs *uart; + uint32_t sys_clk_freq; +}; + +/* Device data structure */ + +struct pl011_data +{ + uint32_t baud_rate; + bool sbsa; +}; + +struct pl011_uart_port_s +{ + struct pl011_data data; + struct pl011_config config; + unsigned int irq_num; + bool is_console; +}; + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +static void pl011_enable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->cr |= PL011_CR_UARTEN; +} + +static void pl011_disable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->cr &= ~PL011_CR_UARTEN; +} + +static void pl011_enable_fifo(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->lcr_h |= PL011_LCRH_FEN; +} + +static void pl011_disable_fifo(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->lcr_h &= ~PL011_LCRH_FEN; +} + +static int pl011_set_baudrate(const struct pl011_uart_port_s *sport, + uint32_t clk, uint32_t baudrate) +{ + const struct pl011_config *config = &sport->config; + + /* Avoiding float calculations, bauddiv is left shifted by 6 */ + + uint64_t bauddiv = + (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U); + + /* Valid bauddiv value + * uart_clk (min) >= 16 x baud_rate (max) + * uart_clk (max) <= 16 x 65535 x baud_rate (min) + */ + + if ((bauddiv < (1U << PL011_FBRD_WIDTH)) || + (bauddiv > (65535U << PL011_FBRD_WIDTH))) + { + return -EINVAL; + } + + config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH; + config->uart->fbrd = bauddiv & ((1U << PL011_FBRD_WIDTH) - 1U); + + __DMB(); + + /* In order to internally update the contents of ibrd or fbrd, a + * lcr_h write must always be performed at the end + * ARM DDI 0183F, Pg 3-13 + */ + + config->uart->lcr_h = config->uart->lcr_h; + + return 0; +} + +static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc |= PL011_IMSC_TXIM; +} + +static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc &= ~PL011_IMSC_TXIM; +} + +static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM; +} + +static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM); +} + +static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + /* check for TX FIFO empty */ + + return config->uart->fr & PL011_FR_TXFE; +} + +static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + const struct pl011_data *data = &sport->data; + + if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE)) + { + return false; + } + + return (config->uart->imsc & PL011_IMSC_RXIM) && + (!(config->uart->fr & PL011_FR_RXFE)); +} + +/*************************************************************************** + * Name: qemu_pl011_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ***************************************************************************/ + +static bool qemu_pl011_txready(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + struct pl011_data *data = &sport->data; + + if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE)) + { + return false; + } + + return (config->uart->imsc & PL011_IMSC_TXIM) && + pl011_irq_tx_complete(sport); +} + +/*************************************************************************** + * Name: qemu_pl011_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ***************************************************************************/ + +static bool qemu_pl011_txempty(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + return pl011_irq_tx_complete(sport); +} + +/*************************************************************************** + * Name: qemu_pl011_send + * + * Description: + * This method will send one byte on the UART + * + ***************************************************************************/ + +static void qemu_pl011_send(struct uart_dev_s *dev, int ch) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + + config->uart->dr = ch; +} + +/*************************************************************************** + * Name: qemu_pl011_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ***************************************************************************/ + +static bool qemu_pl011_rxavailable(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + struct pl011_data *data = &sport->data; + + if (!data->sbsa && + (!(config->uart->cr & PL011_CR_UARTEN) || + !(config->uart->cr & PL011_CR_RXE))) + { + return false; + } + + return (config->uart->fr & PL011_FR_RXFE) == 0U; +} + +/*************************************************************************** + * Name: qemu_pl011_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ***************************************************************************/ + +static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + if (enable) + { + pl011_irq_rx_enable(sport); + } + else + { + pl011_irq_rx_disable(sport); + } +} + +/*************************************************************************** + * Name: qemu_pl011_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ***************************************************************************/ + +static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + if (enable) + { + pl011_irq_tx_enable(sport); + } + else + { + pl011_irq_tx_disable(sport); + } +} + +/*************************************************************************** + * Name: qemu_pl011_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ***************************************************************************/ + +static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + unsigned int rx; + + rx = config->uart->dr; + + *status = 0; + + return rx; +} + +/*************************************************************************** + * Name: qemu_pl011_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * for current qemu configure, + * + ***************************************************************************/ + +static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + int ret = OK; + Review Comment: Maybe add: ``` UNUSED(filep); UNUSED(arg); ``` ########## arch/arm64/src/qemu/qemu_serial.c: ########## @@ -0,0 +1,873 @@ +/*************************************************************************** + * arch/arm64/src/qemu/qemu_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include <nuttx/config.h> +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <unistd.h> +#include <string.h> +#include <assert.h> +#include <errno.h> +#include <debug.h> + +#ifdef CONFIG_SERIAL_TERMIOS +# include <termios.h> +#endif + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <nuttx/spinlock.h> +#include <nuttx/init.h> +#include <nuttx/fs/ioctl.h> +#include <nuttx/semaphore.h> +#include <nuttx/serial/serial.h> + +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "qemu_serial.h" +#include "arm64_arch_timer.h" +#include "qemu_boot.h" +#include "arm64_gic.h" + +#ifdef USE_SERIALDRIVER + +/*************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Which UART with be tty0/console and which tty1-4? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered UART. + */ + +/* First pick the console and ttys0. This could be any of UART1-5 */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#endif + +#define PL011_BIT_MASK(x, y) (((2 << (x)) - 1) << (y)) + +/* PL011 Uart Flags Register */ +#define PL011_FR_CTS BIT(0) /* clear to send - inverted */ +#define PL011_FR_DSR BIT(1) /* data set ready - inverted + */ +#define PL011_FR_DCD BIT(2) /* data carrier detect - + * inverted */ +#define PL011_FR_BUSY BIT(3) /* busy transmitting data */ +#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */ +#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */ +#define PL011_FR_RXFF BIT(6) /* receive FIFO full */ +#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */ +#define PL011_FR_RI BIT(8) /* ring indicator - inverted */ + +/* PL011 Integer baud rate register */ +#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */ + +/* PL011 Fractional baud rate register */ +#define PL011_FBRD_BAUD_DIVFRAC 0x3f +#define PL011_FBRD_WIDTH 6u + +/* PL011 Receive status register / error clear register */ +#define PL011_RSR_ECR_FE BIT(0) /* framing error */ +#define PL011_RSR_ECR_PE BIT(1) /* parity error */ +#define PL011_RSR_ECR_BE BIT(2) /* break error */ +#define PL011_RSR_ECR_OE BIT(3) /* overrun error */ + +#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \ + PL011_RSR_ECR_BE | PL011_RSR_ECR_OE) + +/* PL011 Line Control Register */ +#define PL011_LCRH_BRK BIT(0) /* send break */ +#define PL011_LCRH_PEN BIT(1) /* enable parity */ +#define PL011_LCRH_EPS BIT(2) /* select even parity */ +#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */ +#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */ +#define PL011_LCRH_WLEN_SHIFT 5 /* word length */ +#define PL011_LCRH_WLEN_WIDTH 2 +#define PL011_LCRH_SPS BIT(7) /* stick parity bit */ + +#define PL011_LCRH_WLEN_SIZE(x) ((x) - 5) + +#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \ + PL011_LCRH_SPS | \ + PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \ + PL011_LCRH_WLEN_SHIFT)) + +#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS) +#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN) +#define PL011_LCRH_PARITY_NONE (0) + +/* PL011 Control Register */ +#define PL011_CR_UARTEN BIT(0) /* enable uart operations */ +#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */ +#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */ +#define PL011_CR_LBE BIT(7) /* loop back enable */ +#define PL011_CR_TXE BIT(8) /* transmit enable */ +#define PL011_CR_RXE BIT(9) /* receive enable */ +#define PL011_CR_DTR BIT(10) /* data transmit ready */ +#define PL011_CR_RTS BIT(11) /* request to send */ +#define PL011_CR_Out1 BIT(12) +#define PL011_CR_Out2 BIT(13) +#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable + */ +#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable + */ + +/* PL011 Interrupt Fifo Level Select Register */ +#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */ +#define PL011_IFLS_TXIFLSEL_WIDTH 3 +#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */ +#define PL011_IFLS_RXIFLSEL_WIDTH 3 + +/* PL011 Interrupt Mask Set/Clear Register */ +#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */ +#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */ +#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */ +#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */ +#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */ +#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */ +#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt + * mask */ +#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt + * mask */ +#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask + */ +#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask + */ +#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt + * mask */ + +#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \ + PL011_IMSC_PEIM | PL011_IMSC_BEIM | \ + PL011_IMSC_OEIM) + +#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \ + PL011_IMSC_PEIM | PL011_IMSC_FEIM | \ + PL011_IMSC_RIMIM | \ + PL011_IMSC_CTSMIM | \ + PL011_IMSC_DCDMIM | \ + PL011_IMSC_DSRMIM | \ + PL011_IMSC_RXIM | PL011_IMSC_TXIM | \ + PL011_IMSC_RTIM) + +/*************************************************************************** + * Private Types + ***************************************************************************/ + +/* UART PL011 register map structure */ + +struct pl011_regs +{ + uint32_t dr; /* data register */ + union + { + uint32_t rsr; + uint32_t ecr; + }; + + uint32_t reserved_0[4]; + uint32_t fr; /* flags register */ + uint32_t reserved_1; + uint32_t ilpr; + uint32_t ibrd; + uint32_t fbrd; + uint32_t lcr_h; + uint32_t cr; + uint32_t ifls; + uint32_t imsc; + uint32_t ris; + uint32_t mis; + uint32_t icr; + uint32_t dmacr; +}; + +struct pl011_config +{ + volatile struct pl011_regs *uart; + uint32_t sys_clk_freq; +}; + +/* Device data structure */ + +struct pl011_data +{ + uint32_t baud_rate; + bool sbsa; +}; + +struct pl011_uart_port_s +{ + struct pl011_data data; + struct pl011_config config; + unsigned int irq_num; + bool is_console; +}; + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +static void pl011_enable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->cr |= PL011_CR_UARTEN; +} + +static void pl011_disable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->cr &= ~PL011_CR_UARTEN; +} + +static void pl011_enable_fifo(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->lcr_h |= PL011_LCRH_FEN; +} + +static void pl011_disable_fifo(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->lcr_h &= ~PL011_LCRH_FEN; +} + +static int pl011_set_baudrate(const struct pl011_uart_port_s *sport, + uint32_t clk, uint32_t baudrate) +{ + const struct pl011_config *config = &sport->config; + + /* Avoiding float calculations, bauddiv is left shifted by 6 */ + + uint64_t bauddiv = + (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U); + + /* Valid bauddiv value + * uart_clk (min) >= 16 x baud_rate (max) + * uart_clk (max) <= 16 x 65535 x baud_rate (min) + */ + + if ((bauddiv < (1U << PL011_FBRD_WIDTH)) || + (bauddiv > (65535U << PL011_FBRD_WIDTH))) + { + return -EINVAL; + } + + config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH; + config->uart->fbrd = bauddiv & ((1U << PL011_FBRD_WIDTH) - 1U); + + __DMB(); + + /* In order to internally update the contents of ibrd or fbrd, a + * lcr_h write must always be performed at the end + * ARM DDI 0183F, Pg 3-13 + */ + + config->uart->lcr_h = config->uart->lcr_h; + + return 0; +} + +static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc |= PL011_IMSC_TXIM; +} + +static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc &= ~PL011_IMSC_TXIM; +} + +static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM; +} + +static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM); +} + +static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + /* check for TX FIFO empty */ + + return config->uart->fr & PL011_FR_TXFE; +} + +static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + const struct pl011_data *data = &sport->data; + + if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE)) + { + return false; + } + + return (config->uart->imsc & PL011_IMSC_RXIM) && + (!(config->uart->fr & PL011_FR_RXFE)); +} + +/*************************************************************************** + * Name: qemu_pl011_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ***************************************************************************/ + +static bool qemu_pl011_txready(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + struct pl011_data *data = &sport->data; + + if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE)) + { + return false; + } + + return (config->uart->imsc & PL011_IMSC_TXIM) && + pl011_irq_tx_complete(sport); +} + +/*************************************************************************** + * Name: qemu_pl011_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ***************************************************************************/ + +static bool qemu_pl011_txempty(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + return pl011_irq_tx_complete(sport); +} + +/*************************************************************************** + * Name: qemu_pl011_send + * + * Description: + * This method will send one byte on the UART + * + ***************************************************************************/ + +static void qemu_pl011_send(struct uart_dev_s *dev, int ch) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + + config->uart->dr = ch; +} + +/*************************************************************************** + * Name: qemu_pl011_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ***************************************************************************/ + +static bool qemu_pl011_rxavailable(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + struct pl011_data *data = &sport->data; + + if (!data->sbsa && + (!(config->uart->cr & PL011_CR_UARTEN) || + !(config->uart->cr & PL011_CR_RXE))) + { + return false; + } + + return (config->uart->fr & PL011_FR_RXFE) == 0U; +} + +/*************************************************************************** + * Name: qemu_pl011_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ***************************************************************************/ + +static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + if (enable) + { + pl011_irq_rx_enable(sport); + } + else + { + pl011_irq_rx_disable(sport); + } +} + +/*************************************************************************** + * Name: qemu_pl011_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ***************************************************************************/ + +static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + if (enable) + { + pl011_irq_tx_enable(sport); + } + else + { + pl011_irq_tx_disable(sport); + } +} + +/*************************************************************************** + * Name: qemu_pl011_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ***************************************************************************/ + +static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + unsigned int rx; + + rx = config->uart->dr; + + *status = 0; + + return rx; +} + +/*************************************************************************** + * Name: qemu_pl011_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * for current qemu configure, + * + ***************************************************************************/ + +static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + int ret = OK; + + switch (cmd) + { + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + { + ret = -ENOTTY; + break; + } + } + + return ret; +} + +/*************************************************************************** + * Name: qemu_pl011_irq_handler (and front-ends) + * + * Description: + * This is the common UART interrupt handler. It should cal + * uart_transmitchars or uart_receivechar to perform the appropriate data + * transfers. + * + ***************************************************************************/ + +static int qemu_pl011_irq_handler(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct pl011_uart_port_s *sport; + Review Comment: Maybe add: ``` UNUSED(irq); UNUSED(context); ``` ########## arch/arm64/src/common/arm64_fpu.c: ########## @@ -0,0 +1,240 @@ +/*************************************************************************** + * arch/arm64/src/common/arm64_fpu.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include <nuttx/config.h> + +#include <inttypes.h> +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <errno.h> +#include <debug.h> +#include <nuttx/sched.h> +#include <nuttx/arch.h> +#include <arch/irq.h> + +#include "sched/sched.h" +#include "arm64_arch.h" +#include "arm64_vfork.h" +#include "arm64_internal.h" +#include "arm64_fatal.h" +#include "arm64_fpu.h" + +/*************************************************************************** + * Private Data + ***************************************************************************/ + +static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS]; +static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS]; + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +/* enable FPU access trap */ + +static void arm64_fpu_access_trap_enable(void) +{ + uint64_t cpacr; + + cpacr = read_sysreg(cpacr_el1); + cpacr &= ~CPACR_EL1_FPEN_NOTRAP; + write_sysreg(cpacr, cpacr_el1); + + __ISB(); +} + +/* disable FPU access trap */ + +static void arm64_fpu_access_trap_disable(void) +{ + uint64_t cpacr; + + cpacr = read_sysreg(cpacr_el1); + cpacr |= CPACR_EL1_FPEN_NOTRAP; + write_sysreg(cpacr, cpacr_el1); + + __ISB(); +} + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +void arm64_init_fpu(struct tcb_s *tcb) +{ + struct fpu_reg *fpu_reg; + + if (tcb->pid < CONFIG_SMP_NCPUS) + { + memset(&g_cpu_fpu_ctx[this_cpu()], 0, + sizeof(struct arm64_cpu_fpu_context)); + g_cpu_fpu_ctx[this_cpu()].idle_thread = tcb; + + tcb->xcp.fpu_regs = (uint64_t *)&g_idle_thread_fpu[this_cpu()]; + } + + memset(tcb->xcp.fpu_regs, 0, sizeof(struct fpu_reg)); + fpu_reg = (struct fpu_reg *)tcb->xcp.fpu_regs; + fpu_reg->fpu_trap = 0; +} + +void arm64_destory_fpu(struct tcb_s * tcb) +{ + struct tcb_s * owner; + + /* save current fpu owner's context */ + + owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner; + + if (owner == tcb) + { + g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL; + } +} + +/*************************************************************************** + * Name: arm64_fpu_enter_exception + * + * Description: + * called at every time get into a exception + * + ***************************************************************************/ + +void arm64_fpu_enter_exception(void) +{ +} + +void arm64_fpu_exit_exception(void) +{ +} + +void arm64_fpu_trap(struct regs_context * regs) +{ + struct tcb_s * owner; + struct fpu_reg *fpu_reg; + Review Comment: Maybe add: `UNUSED(regs);` ########## arch/arm64/src/common/arm64_exit.c: ########## @@ -0,0 +1,157 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_exit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sched.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <nuttx/irq.h> +#ifdef CONFIG_DUMP_ON_EXIT +# include <nuttx/fs/fs.h> +#endif + +#include "task/task.h" +#include "sched/sched.h" +#include "group/group.h" +#include "irq/irq.h" +#include "arm64_internal.h" + +#ifdef CONFIG_ARCH_FPU +#include "arm64_fpu.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _up_dumponexit + * + * Description: + * Dump the state of all tasks whenever on task exits. This is debug + * instrumentation that was added to check file-related reference counting + * but could be useful again sometime in the future. + * + ****************************************************************************/ + +#ifdef CONFIG_DUMP_ON_EXIT +static void _up_dumponexit(struct tcb_s *tcb, void *arg) +{ + struct filelist *filelist; + int i; + int j; + + sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->name, tcb->pid); + sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + + filelist = tcb->group->tg_filelist; + for (i = 0; i < filelist->fl_rows; i++) + { + for (j = 0; j < CONFIG_NFILE_DESCRIPTORS_PER_BLOCK; j++) + { + struct inode *inode = filelist->fl_files[i][j].f_inode; + if (inode) + { + sinfo(" fd=%d refcount=%d\n", + i * CONFIG_NFILE_DESCRIPTORS_PER_BLOCK + j, + inode->i_crefs); + } + } + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_exit + * + * Description: + * This function causes the currently executing task to cease + * to exist. This is a special case of task_delete() where the task to + * be deleted is the currently executing task. It is more complex because + * a context switch must be perform to the next ready to run task. + * + ****************************************************************************/ + +void up_exit(int status) +{ + struct tcb_s *tcb = this_task(); + Review Comment: Maybe add: `UNUSED(status); ` ########## arch/arm64/src/common/arm64_arch_timer.c: ########## @@ -0,0 +1,253 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_arch_timer.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <debug.h> +#include <assert.h> + +#include <nuttx/arch.h> +#include <arch/irq.h> +#include <arch/chip/chip.h> +#include <nuttx/spinlock.h> + +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "arm64_gic.h" +#include "arm64_arch_timer.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +#define MIN_DELAY (1000) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint64_t last_cycle; +static uint64_t cycle_per_tick; +static uint32_t arch_timer_rate; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void arm64_arch_timer_set_compare(uint64_t value) +{ + write_sysreg(value, cntv_cval_el0); +} + +static inline void arm64_arch_timer_enable(unsigned char enable) +{ + uint64_t value; + + value = read_sysreg(cntv_ctl_el0); + + if (enable) + { + value |= CNTV_CTL_ENABLE_BIT; + } + else + { + value &= ~CNTV_CTL_ENABLE_BIT; + } + + write_sysreg(value, cntv_ctl_el0); +} + +static inline void arm64_arch_timer_set_irq_mask(bool mask) +{ + uint64_t value; + + value = read_sysreg(cntv_ctl_el0); + + if (mask) + { + value |= CNTV_CTL_IMASK_BIT; + } + else + { + value &= ~CNTV_CTL_IMASK_BIT; + } + + write_sysreg(value, cntv_ctl_el0); +} + +static inline uint64_t arm64_arch_timer_count(void) +{ + return read_sysreg(cntvct_el0); +} + +static inline uint32_t arm64_arch_timer_get_cntfrq(void) +{ + return read_sysreg(cntfrq_el0); +} + +#ifdef CONFIG_SCHED_TICKLESS +static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg) +{ + irqstate_t flags; + uint64_t curr_cycle; + uint32_t delta_ticks; + + UNUSED(regs); + UNUSED(arg); + + flags = spin_lock_irqsave(&g_arch_timer_lock); + + curr_cycle = arm64_arch_timer_count(); + delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick); + + last_cycle += delta_ticks * cycle_per_tick; + + arm_arch_timer_set_irq_mask(true); + + spin_unlock_irqrestore(&g_arch_timer_lock, flags); + + nxsched_process_timer(); + return OK; +} + +#else + +static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg) +{ + uint64_t curr_cycle; + uint32_t delta_ticks; + uint64_t next_cycle; + + UNUSED(regs); + UNUSED(arg); + Review Comment: Also add here `UNUSED(irq);` ########## arch/arm64/src/qemu/qemu_serial.c: ########## @@ -0,0 +1,873 @@ +/*************************************************************************** + * arch/arm64/src/qemu/qemu_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include <nuttx/config.h> +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <unistd.h> +#include <string.h> +#include <assert.h> +#include <errno.h> +#include <debug.h> + +#ifdef CONFIG_SERIAL_TERMIOS +# include <termios.h> +#endif + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <nuttx/spinlock.h> +#include <nuttx/init.h> +#include <nuttx/fs/ioctl.h> +#include <nuttx/semaphore.h> +#include <nuttx/serial/serial.h> + +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "qemu_serial.h" +#include "arm64_arch_timer.h" +#include "qemu_boot.h" +#include "arm64_gic.h" + +#ifdef USE_SERIALDRIVER + +/*************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Which UART with be tty0/console and which tty1-4? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered UART. + */ + +/* First pick the console and ttys0. This could be any of UART1-5 */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#endif + +#define PL011_BIT_MASK(x, y) (((2 << (x)) - 1) << (y)) + +/* PL011 Uart Flags Register */ +#define PL011_FR_CTS BIT(0) /* clear to send - inverted */ +#define PL011_FR_DSR BIT(1) /* data set ready - inverted + */ +#define PL011_FR_DCD BIT(2) /* data carrier detect - + * inverted */ +#define PL011_FR_BUSY BIT(3) /* busy transmitting data */ +#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */ +#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */ +#define PL011_FR_RXFF BIT(6) /* receive FIFO full */ +#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */ +#define PL011_FR_RI BIT(8) /* ring indicator - inverted */ + +/* PL011 Integer baud rate register */ +#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */ + +/* PL011 Fractional baud rate register */ +#define PL011_FBRD_BAUD_DIVFRAC 0x3f +#define PL011_FBRD_WIDTH 6u + +/* PL011 Receive status register / error clear register */ +#define PL011_RSR_ECR_FE BIT(0) /* framing error */ +#define PL011_RSR_ECR_PE BIT(1) /* parity error */ +#define PL011_RSR_ECR_BE BIT(2) /* break error */ +#define PL011_RSR_ECR_OE BIT(3) /* overrun error */ + +#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \ + PL011_RSR_ECR_BE | PL011_RSR_ECR_OE) + +/* PL011 Line Control Register */ +#define PL011_LCRH_BRK BIT(0) /* send break */ +#define PL011_LCRH_PEN BIT(1) /* enable parity */ +#define PL011_LCRH_EPS BIT(2) /* select even parity */ +#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */ +#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */ +#define PL011_LCRH_WLEN_SHIFT 5 /* word length */ +#define PL011_LCRH_WLEN_WIDTH 2 +#define PL011_LCRH_SPS BIT(7) /* stick parity bit */ + +#define PL011_LCRH_WLEN_SIZE(x) ((x) - 5) + +#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \ + PL011_LCRH_SPS | \ + PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \ + PL011_LCRH_WLEN_SHIFT)) + +#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS) +#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN) +#define PL011_LCRH_PARITY_NONE (0) + +/* PL011 Control Register */ +#define PL011_CR_UARTEN BIT(0) /* enable uart operations */ +#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */ +#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */ +#define PL011_CR_LBE BIT(7) /* loop back enable */ +#define PL011_CR_TXE BIT(8) /* transmit enable */ +#define PL011_CR_RXE BIT(9) /* receive enable */ +#define PL011_CR_DTR BIT(10) /* data transmit ready */ +#define PL011_CR_RTS BIT(11) /* request to send */ +#define PL011_CR_Out1 BIT(12) +#define PL011_CR_Out2 BIT(13) +#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable + */ +#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable + */ + +/* PL011 Interrupt Fifo Level Select Register */ +#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */ +#define PL011_IFLS_TXIFLSEL_WIDTH 3 +#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */ +#define PL011_IFLS_RXIFLSEL_WIDTH 3 + +/* PL011 Interrupt Mask Set/Clear Register */ +#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */ +#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */ +#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */ +#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */ +#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */ +#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */ +#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt + * mask */ +#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt + * mask */ +#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask + */ +#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask + */ +#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt + * mask */ + +#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \ + PL011_IMSC_PEIM | PL011_IMSC_BEIM | \ + PL011_IMSC_OEIM) + +#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \ + PL011_IMSC_PEIM | PL011_IMSC_FEIM | \ + PL011_IMSC_RIMIM | \ + PL011_IMSC_CTSMIM | \ + PL011_IMSC_DCDMIM | \ + PL011_IMSC_DSRMIM | \ + PL011_IMSC_RXIM | PL011_IMSC_TXIM | \ + PL011_IMSC_RTIM) + +/*************************************************************************** + * Private Types + ***************************************************************************/ + +/* UART PL011 register map structure */ + +struct pl011_regs +{ + uint32_t dr; /* data register */ + union + { + uint32_t rsr; + uint32_t ecr; + }; + + uint32_t reserved_0[4]; + uint32_t fr; /* flags register */ + uint32_t reserved_1; + uint32_t ilpr; + uint32_t ibrd; + uint32_t fbrd; + uint32_t lcr_h; + uint32_t cr; + uint32_t ifls; + uint32_t imsc; + uint32_t ris; + uint32_t mis; + uint32_t icr; + uint32_t dmacr; +}; + +struct pl011_config +{ + volatile struct pl011_regs *uart; + uint32_t sys_clk_freq; +}; + +/* Device data structure */ + +struct pl011_data +{ + uint32_t baud_rate; + bool sbsa; +}; + +struct pl011_uart_port_s +{ + struct pl011_data data; + struct pl011_config config; + unsigned int irq_num; + bool is_console; +}; + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +static void pl011_enable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->cr |= PL011_CR_UARTEN; +} + +static void pl011_disable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->cr &= ~PL011_CR_UARTEN; +} + +static void pl011_enable_fifo(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->lcr_h |= PL011_LCRH_FEN; +} + +static void pl011_disable_fifo(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->lcr_h &= ~PL011_LCRH_FEN; +} + +static int pl011_set_baudrate(const struct pl011_uart_port_s *sport, + uint32_t clk, uint32_t baudrate) +{ + const struct pl011_config *config = &sport->config; + + /* Avoiding float calculations, bauddiv is left shifted by 6 */ + + uint64_t bauddiv = + (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U); + + /* Valid bauddiv value + * uart_clk (min) >= 16 x baud_rate (max) + * uart_clk (max) <= 16 x 65535 x baud_rate (min) + */ + + if ((bauddiv < (1U << PL011_FBRD_WIDTH)) || + (bauddiv > (65535U << PL011_FBRD_WIDTH))) + { + return -EINVAL; + } + + config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH; + config->uart->fbrd = bauddiv & ((1U << PL011_FBRD_WIDTH) - 1U); + + __DMB(); + + /* In order to internally update the contents of ibrd or fbrd, a + * lcr_h write must always be performed at the end + * ARM DDI 0183F, Pg 3-13 + */ + + config->uart->lcr_h = config->uart->lcr_h; + + return 0; +} + +static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc |= PL011_IMSC_TXIM; +} + +static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc &= ~PL011_IMSC_TXIM; +} + +static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM; +} + +static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM); +} + +static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + + /* check for TX FIFO empty */ + + return config->uart->fr & PL011_FR_TXFE; +} + +static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport) +{ + const struct pl011_config *config = &sport->config; + const struct pl011_data *data = &sport->data; + + if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE)) + { + return false; + } + + return (config->uart->imsc & PL011_IMSC_RXIM) && + (!(config->uart->fr & PL011_FR_RXFE)); +} + +/*************************************************************************** + * Name: qemu_pl011_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ***************************************************************************/ + +static bool qemu_pl011_txready(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + struct pl011_data *data = &sport->data; + + if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE)) + { + return false; + } + + return (config->uart->imsc & PL011_IMSC_TXIM) && + pl011_irq_tx_complete(sport); +} + +/*************************************************************************** + * Name: qemu_pl011_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ***************************************************************************/ + +static bool qemu_pl011_txempty(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + return pl011_irq_tx_complete(sport); +} + +/*************************************************************************** + * Name: qemu_pl011_send + * + * Description: + * This method will send one byte on the UART + * + ***************************************************************************/ + +static void qemu_pl011_send(struct uart_dev_s *dev, int ch) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + + config->uart->dr = ch; +} + +/*************************************************************************** + * Name: qemu_pl011_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ***************************************************************************/ + +static bool qemu_pl011_rxavailable(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + struct pl011_data *data = &sport->data; + + if (!data->sbsa && + (!(config->uart->cr & PL011_CR_UARTEN) || + !(config->uart->cr & PL011_CR_RXE))) + { + return false; + } + + return (config->uart->fr & PL011_FR_RXFE) == 0U; +} + +/*************************************************************************** + * Name: qemu_pl011_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ***************************************************************************/ + +static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + if (enable) + { + pl011_irq_rx_enable(sport); + } + else + { + pl011_irq_rx_disable(sport); + } +} + +/*************************************************************************** + * Name: qemu_pl011_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ***************************************************************************/ + +static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + if (enable) + { + pl011_irq_tx_enable(sport); + } + else + { + pl011_irq_tx_disable(sport); + } +} + +/*************************************************************************** + * Name: qemu_pl011_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ***************************************************************************/ + +static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + const struct pl011_config *config = &sport->config; + unsigned int rx; + + rx = config->uart->dr; + + *status = 0; + + return rx; +} + +/*************************************************************************** + * Name: qemu_pl011_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * for current qemu configure, + * + ***************************************************************************/ + +static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + int ret = OK; + + switch (cmd) + { + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + { + ret = -ENOTTY; + break; + } + } + + return ret; +} + +/*************************************************************************** + * Name: qemu_pl011_irq_handler (and front-ends) + * + * Description: + * This is the common UART interrupt handler. It should cal + * uart_transmitchars or uart_receivechar to perform the appropriate data + * transfers. + * + ***************************************************************************/ + +static int qemu_pl011_irq_handler(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct pl011_uart_port_s *sport; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + sport = (struct pl011_uart_port_s *)dev->priv; + + if (pl011_irq_rx_ready(sport)) + { + uart_recvchars(dev); + } + + if (qemu_pl011_txready(dev)) + { + uart_xmitchars(dev); + } + + return OK; +} + +/*************************************************************************** + * Name: qemu_pl011_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ***************************************************************************/ + +static void qemu_pl011_detach(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; + + up_disable_irq(sport->irq_num); + irq_detach(sport->irq_num); +} + +/*************************************************************************** + * Name: qemu_pl011_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. + * This method is called when the serial port is opened. + * Normally, this is just after the setup() method is called, + * however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method + * (unless the hardware supports multiple levels of interrupt + * enabling). The RX and TX interrupts are not enabled until + * the txint() and rxint() methods are called. + * + ***************************************************************************/ + +static int qemu_pl011_attach(struct uart_dev_s *dev) +{ + struct pl011_uart_port_s *sport; + struct pl011_data *data; + int ret; + + sport = (struct pl011_uart_port_s *)dev->priv; + data = &sport->data; + + ret = irq_attach(sport->irq_num, qemu_pl011_irq_handler, dev); + arm64_gic_irq_set_priority(sport->irq_num, IRQ_TYPE_LEVEL, 0); + + if (ret == OK) + { + up_enable_irq(sport->irq_num); + } + else + { + sinfo("error ret=%d\n", ret); + } + + if (!data->sbsa) + { + pl011_enable(sport); + } + + return ret; +} + +/*************************************************************************** + * Name: qemu_pl011_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ***************************************************************************/ + +static void qemu_pl011_shutdown(struct uart_dev_s *dev) +{ + sinfo("%s: call unexpected\n", __func__); Review Comment: Add `UNUSED(dev); ` -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
