qinwei2004 commented on code in PR #6478: URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915846897
########## arch/arm64/include/irq.h: ########## @@ -0,0 +1,435 @@ +/**************************************************************************** + * arch/arm64/include/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM64_INCLUDE_IRQ_H +#define __ARCH_ARM64_INCLUDE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include NuttX-specific IRQ definitions */ + +#include <nuttx/irq.h> + +/* Include chip-specific IRQ definitions (including IRQ numbers) */ + +#include <arch/chip/irq.h> + +#include <nuttx/config.h> + +#ifndef __ASSEMBLY__ +# include <stdint.h> +# include <arch/arch.h> +#endif + +/**************************************************************************** + * Exception stack frame format: + * + * x0 ~ x18, x30 (lr), spsr and elr + * Corruptible Registers and exception context + * reference to Armv8-A Instruction Set Architecture + * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS + * need to be saved in all exception + * + * x19 ~ x29, sp_el0, sp_elx + * Callee-saved Registers and SP pointer + * reference to Armv8-A Instruction Set Architecture + * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS + * These registers frame is allocated on stack frame + * when a exception is occurred and saved at task switch + * or crash exception + * check arm64_vectors.S for detail + * + ****************************************************************************/ + +/**************************************************************************** + * Registers and exception context + * Note: + * REG_EXEC_DEPTH indicate the task's exception depth + * + ****************************************************************************/ + +#define REG_X0 (0) +#define REG_X1 (1) +#define REG_X2 (2) +#define REG_X3 (3) +#define REG_X4 (4) +#define REG_X5 (5) +#define REG_X6 (6) +#define REG_X7 (7) +#define REG_X8 (8) +#define REG_X9 (9) +#define REG_X10 (10) +#define REG_X11 (11) +#define REG_X12 (12) +#define REG_X13 (13) +#define REG_X14 (14) +#define REG_X15 (15) +#define REG_X16 (16) +#define REG_X17 (17) +#define REG_X18 (18) +#define REG_X19 (19) +#define REG_X20 (20) +#define REG_X21 (21) +#define REG_X22 (22) +#define REG_X23 (23) +#define REG_X24 (24) +#define REG_X25 (25) +#define REG_X26 (26) +#define REG_X27 (27) +#define REG_X28 (28) +#define REG_X29 (29) +#define REG_X30 (30) +#define REG_SP_ELX (31) +#define REG_ELR (32) +#define REG_SPSR (33) +#define REG_SP_EL0 (34) +#define REG_EXE_DEPTH (35) +#define REG_TPIDR_EL0 (36) +#define REG_TPIDR_EL1 (37) + +/* In Armv8-A Architecture, the stack must align with 16 byte */ + +#define XCPTCONTEXT_GP_REGS (38) +#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS) + +#ifdef CONFIG_ARCH_FPU + +/**************************************************************************** + * q0 ~ q31(128bit), fpsr, fpcr + * armv8 fpu registers and context + * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context + * is allocated on stack frame at exception and store/restore + * when switching FPU context + * check arm64_fpu.c for detail + * + ****************************************************************************/ + +/* 128bit registers */ + +#define FPU_REG_Q0 (0) +#define FPU_REG_Q1 (1) +#define FPU_REG_Q2 (2) +#define FPU_REG_Q3 (3) +#define FPU_REG_Q4 (4) +#define FPU_REG_Q5 (5) +#define FPU_REG_Q6 (6) +#define FPU_REG_Q7 (7) +#define FPU_REG_Q8 (8) +#define FPU_REG_Q9 (9) +#define FPU_REG_Q10 (10) +#define FPU_REG_Q11 (11) +#define FPU_REG_Q12 (12) +#define FPU_REG_Q13 (13) +#define FPU_REG_Q14 (14) +#define FPU_REG_Q15 (15) +#define FPU_REG_Q16 (16) +#define FPU_REG_Q17 (17) +#define FPU_REG_Q18 (18) +#define FPU_REG_Q19 (19) +#define FPU_REG_Q20 (20) +#define FPU_REG_Q21 (21) +#define FPU_REG_Q22 (22) +#define FPU_REG_Q23 (23) +#define FPU_REG_Q24 (24) +#define FPU_REG_Q25 (25) +#define FPU_REG_Q26 (26) +#define FPU_REG_Q27 (27) +#define FPU_REG_Q28 (28) +#define FPU_REG_Q29 (29) +#define FPU_REG_Q30 (30) +#define FPU_REG_Q31 (31) + +/* 32 bit registers + */ +#define FPU_REG_FPSR (0) +#define FPU_REG_FPCR (1) + +/* FPU registers(Q0~Q31, 128bit): 32x2 = 64 + * FPU FPSR/SPSR(32 bit) : 1 + * FPU TRAP: 1 + * 64 + 1 + 1 = 66 + */ +#define ARM64_FPU_REGS (66) Review Comment: done -- This is an automated message from the Apache Git Service. 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