pkarashchenko commented on code in PR #6478: URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902289974
########## arch/arm64/include/syscall.h: ########## @@ -0,0 +1,390 @@ +/**************************************************************************** + * arch/arm64/include/syscall.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H +#define __ARCH_ARM64_INCLUDE_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#ifndef __ASSEMBLY__ +# include <stdint.h> +#endif + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#define SYS_syscall 0x00 +#define SYS_smhcall 0x123456 + +/* Configuration ************************************************************/ + +/* This logic uses three system calls {0,1,2} for context switching and one + * for the syscall return. + * So a minimum of four syscall values must be reserved. + * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must + * be reserved. + */ + +#ifndef CONFIG_BUILD_FLAT +# define CONFIG_SYS_RESERVED 8 +#else +# define CONFIG_SYS_RESERVED 4 +#endif + +/* system calls */ + +/* SYS call 0: + * + * int arm64_saveusercontext(void *saveregs); + */ + +#define SYS_save_context (0) + +/* SYS call 1: + * + * void arm64_fullcontextrestore(void *restoreregs) noreturn_function; + */ + +#define SYS_restore_context (1) + +/* SYS call 2: + * + * void arm64_switchcontext(void *saveregs, void *restoreregs); + */ + +#define SYS_switch_context (2) + +#ifdef CONFIG_LIB_SYSCALL +/* SYS call 3: + * + * void arm_syscall_return(void); + */ + +#define SYS_syscall_return (3) +#endif /* CONFIG_LIB_SYSCALL */ + +#ifndef CONFIG_BUILD_FLAT +/* SYS call 4: + * + * void up_task_start(main_t taskentry, int argc, char *argv[]) + * noreturn_function; + */ + +#define SYS_task_start (4) + +/* SYS call 5: + * + * void up_pthread_start((pthread_startroutine_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) + * noreturn_function + */ + +#define SYS_pthread_start (5) + +/* SYS call 6: + * + * void signal_handler(_sa_sigaction_t sighand, + * int signo, siginfo_t *info, + * void *ucontext); + */ + +#define SYS_signal_handler (6) + +/* SYS call 7: + * + * void signal_handler_return(void); + */ + +#define SYS_signal_handler_return (7) +#endif /* !CONFIG_BUILD_FLAT */ + +#define ARM_SMCC_RES_A0 (0) +#define ARM_SMCC_RES_A1 (1) +#define ARM_SMCC_RES_A2 (2) +#define ARM_SMCC_RES_A3 (3) +#define ARM_SMCC_RES_A4 (4) +#define ARM_SMCC_RES_A5 (5) +#define ARM_SMCC_RES_A6 (6) +#define ARM_SMCC_RES_A7 (7) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* SVC with SYS_ call number and no parameters */ + +static inline uintptr_t sys_call0(unsigned int nbr) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and one parameter */ + +static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and two parameters */ + +static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and three parameters */ + +static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and four parameters */ + +static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4); + register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and five parameters */ + +static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4, uintptr_t parm5) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5); + register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4); + register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4), "r"(reg5) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and six parameters */ + +static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4, uintptr_t parm5, + uintptr_t parm6) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6); + register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5); + register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4); + register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6) + : "memory", "x30" + ); + + return reg0; +} + +/* semihosting(SMH) call with call number and one parameter */ + +static inline long smh_call(unsigned int nbr, uintptr_t *parm) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm); + + __asm__ __volatile__ + ( + "hlt %1" + : "=r"(reg0) + : "i"(SYS_smhcall), "r"(reg0), "r"(reg1) + : "memory", "x30" + ); + + return reg0; +} + +/* Result from SMC/HVC call + * a0-a7 result values from registers 0 to 7 + */ + +struct arm64_smccc_res +{ + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; +}; + +typedef struct arm64_smccc_res arm64_smccc_res_t; + +enum arm64_smccc_conduit +{ + SMCCC_CONDUIT_NONE, + SMCCC_CONDUIT_SMC, + SMCCC_CONDUIT_HVC, +}; + +/* Make HVC calls + * + * param a0 function identifier + * param a1-a7 parameters registers + * param res results + */ + +void arm64_smccc_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm64_smccc_res *res); Review Comment: ```suggestion void arm64_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, struct arm64_smccc_res *res); ``` ########## arch/arm64/include/syscall.h: ########## @@ -0,0 +1,390 @@ +/**************************************************************************** + * arch/arm64/include/syscall.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H +#define __ARCH_ARM64_INCLUDE_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#ifndef __ASSEMBLY__ +# include <stdint.h> +#endif + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#define SYS_syscall 0x00 +#define SYS_smhcall 0x123456 + +/* Configuration ************************************************************/ + +/* This logic uses three system calls {0,1,2} for context switching and one + * for the syscall return. + * So a minimum of four syscall values must be reserved. + * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must + * be reserved. + */ + +#ifndef CONFIG_BUILD_FLAT +# define CONFIG_SYS_RESERVED 8 +#else +# define CONFIG_SYS_RESERVED 4 +#endif + +/* system calls */ + +/* SYS call 0: + * + * int arm64_saveusercontext(void *saveregs); + */ + +#define SYS_save_context (0) + +/* SYS call 1: + * + * void arm64_fullcontextrestore(void *restoreregs) noreturn_function; + */ + +#define SYS_restore_context (1) + +/* SYS call 2: + * + * void arm64_switchcontext(void *saveregs, void *restoreregs); + */ + +#define SYS_switch_context (2) + +#ifdef CONFIG_LIB_SYSCALL +/* SYS call 3: + * + * void arm_syscall_return(void); + */ + +#define SYS_syscall_return (3) +#endif /* CONFIG_LIB_SYSCALL */ + +#ifndef CONFIG_BUILD_FLAT +/* SYS call 4: + * + * void up_task_start(main_t taskentry, int argc, char *argv[]) + * noreturn_function; + */ + +#define SYS_task_start (4) + +/* SYS call 5: + * + * void up_pthread_start((pthread_startroutine_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) + * noreturn_function + */ + +#define SYS_pthread_start (5) + +/* SYS call 6: + * + * void signal_handler(_sa_sigaction_t sighand, + * int signo, siginfo_t *info, + * void *ucontext); + */ + +#define SYS_signal_handler (6) + +/* SYS call 7: + * + * void signal_handler_return(void); + */ + +#define SYS_signal_handler_return (7) +#endif /* !CONFIG_BUILD_FLAT */ + +#define ARM_SMCC_RES_A0 (0) +#define ARM_SMCC_RES_A1 (1) +#define ARM_SMCC_RES_A2 (2) +#define ARM_SMCC_RES_A3 (3) +#define ARM_SMCC_RES_A4 (4) +#define ARM_SMCC_RES_A5 (5) +#define ARM_SMCC_RES_A6 (6) +#define ARM_SMCC_RES_A7 (7) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* SVC with SYS_ call number and no parameters */ + +static inline uintptr_t sys_call0(unsigned int nbr) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and one parameter */ + +static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and two parameters */ + +static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and three parameters */ + +static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and four parameters */ + +static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4); + register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and five parameters */ + +static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4, uintptr_t parm5) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5); + register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4); + register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4), "r"(reg5) + : "memory", "x30" + ); + + return reg0; +} + +/* SVC with SYS_ call number and six parameters */ + +static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4, uintptr_t parm5, + uintptr_t parm6) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6); + register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5); + register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4); + register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3); + register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1); + + __asm__ __volatile__ + ( + "svc %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6) + : "memory", "x30" + ); + + return reg0; +} + +/* semihosting(SMH) call with call number and one parameter */ + +static inline long smh_call(unsigned int nbr, uintptr_t *parm) +{ + register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr); + register uint64_t reg1 __asm__("x1") = (uint64_t)(parm); + + __asm__ __volatile__ + ( + "hlt %1" + : "=r"(reg0) + : "i"(SYS_smhcall), "r"(reg0), "r"(reg1) + : "memory", "x30" + ); + + return reg0; +} + +/* Result from SMC/HVC call + * a0-a7 result values from registers 0 to 7 + */ + +struct arm64_smccc_res +{ + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; +}; + +typedef struct arm64_smccc_res arm64_smccc_res_t; + +enum arm64_smccc_conduit +{ + SMCCC_CONDUIT_NONE, + SMCCC_CONDUIT_SMC, + SMCCC_CONDUIT_HVC, +}; + +/* Make HVC calls + * + * param a0 function identifier + * param a1-a7 parameters registers + * param res results + */ + +void arm64_smccc_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm64_smccc_res *res); + +/* Make SMC calls + * + * param a0 function identifier + * param a1-a7 parameters registers + * param res results + */ + +void arm64_smccc_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, + struct arm64_smccc_res *res); Review Comment: ```suggestion void arm64_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, struct arm64_smccc_res *res); ``` ########## arch/arm64/src/common/arm64_copystate.c: ########## @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_copystate.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <sched.h> +#include <debug.h> +#include <assert.h> +#include <nuttx/arch.h> +#include <nuttx/sched.h> +#include <arch/syscall.h> +#include <arch/irq.h> + +#include "arm64_internal.h" + +#ifdef CONFIG_ARCH_FPU +#include "arm64_fpu.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +int arch_save_fpucontext(void *saveregs) +{ + irqstate_t flags; + uint64_t * p_save; + + /* Take a snapshot of the thread context right now */ + + flags = enter_critical_section(); + + p_save = saveregs + XCPTCONTEXT_GP_SIZE; + arm64_fpu_save((struct fpu_reg *)p_save); + __DSB(); + + leave_critical_section(flags); + return 0; +} +#endif + +int arm64_syscall_save_context(uint64_t * regs) +{ + struct regs_context * f_regs; + uint64_t * p_save; + int i; + +#ifdef CONFIG_ARCH_FPU + uint64_t * p_fpu; + struct tcb_s * rtcb; + struct tcb_s * rtcb_cur = (struct tcb_s *)arch_get_current_tcb(); Review Comment: ```suggestion struct regs_context *f_regs; uint64_t *p_save; int i; #ifdef CONFIG_ARCH_FPU uint64_t *p_fpu; struct tcb_s *rtcb; struct tcb_s *rtcb_cur = (struct tcb_s *)arch_get_current_tcb(); ``` ########## arch/arm64/src/common/arm64_fpu.c: ########## @@ -0,0 +1,249 @@ +/*************************************************************************** + * arch/arm64/src/common/arm64_fpu.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include <nuttx/config.h> + +#include <inttypes.h> +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <errno.h> +#include <debug.h> +#include <nuttx/sched.h> +#include <nuttx/arch.h> +#include <arch/irq.h> + +#include "sched/sched.h" +#include "arm64_arch.h" +#include "arm64_vfork.h" +#include "arm64_internal.h" +#include "arm64_fatal.h" +#include "arm64_fpu.h" + +static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS]; + +struct arm64_cpu_fpu_context +{ + /* owner of current CPU's FPU */ + + struct tcb_s * fpu_owner; + + struct tcb_s * idle_thread; + + /* for statistic propose */ + + int save_count; + int restore_count; + int switch_count; + int exe_depth_count; +}; + +static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS]; + +/*************************************************************************** + * Private Data + ***************************************************************************/ + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +void arm64_init_fpu(struct tcb_s *tcb) +{ + if (tcb->pid < CONFIG_SMP_NCPUS) + { + memset(&g_cpu_fpu_ctx[this_cpu()], 0, + sizeof(struct arm64_cpu_fpu_context)); + g_cpu_fpu_ctx[this_cpu()].idle_thread = tcb; + + tcb->xcp.fpu_regs = &g_idle_thread_fpu[this_cpu()]; + } + + memset(tcb->xcp.fpu_regs, 0, sizeof(struct fpu_reg)); + tcb->xcp.fpu_regs->fpu_trap = 0; +} + +void arm64_destory_fpu(struct tcb_s * tcb) +{ + struct tcb_s * owner; + + /* save current fpu owner's context */ + + owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner; + + if (owner == tcb) + { + g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL; + } +} + +/* enable FPU access trap */ + +static void arm64_fpu_access_trap_enable(void) +{ + uint64_t cpacr; + + cpacr = read_sysreg(cpacr_el1); + cpacr &= ~CPACR_EL1_FPEN_NOTRAP; + write_sysreg(cpacr, cpacr_el1); + + __ISB(); +} + +/* disable FPU access trap */ + +static void arm64_fpu_access_trap_disable(void) +{ + uint64_t cpacr; + + cpacr = read_sysreg(cpacr_el1); + + cpacr |= CPACR_EL1_FPEN_NOTRAP; + + write_sysreg(cpacr, cpacr_el1); + + __ISB(); +} + +/*************************************************************************** + * Name: arm64_fpu_enter_exception + * + * Description: + * called at every time get into a exception + * + ***************************************************************************/ + +void arm64_fpu_enter_exception(void) +{ +} + +void arm64_fpu_exit_exception(void) +{ +} + +void arm64_fpu_trap(struct esf_reg * regs) +{ + struct tcb_s * owner; + + /* disable fpu trap access */ + + arm64_fpu_access_trap_disable(); + + /* save current fpu owner's context */ + + owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner; + + if (owner != NULL) + { + arm64_fpu_save(owner->xcp.fpu_regs); + __DSB(); + g_cpu_fpu_ctx[this_cpu()].save_count++; + g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL; + } + + if (arch_get_exception_depth() > 1) + { + /* if get_exception_depth > 1 + * it means FPU access exception occurred in exception context + * switch FPU owner to idle thread + */ + + owner = g_cpu_fpu_ctx[this_cpu()].idle_thread; + } + else + { + owner = (struct tcb_s *)arch_get_current_tcb(); + } + + /* restore our content */ + + arm64_fpu_restore(owner->xcp.fpu_regs); + g_cpu_fpu_ctx[this_cpu()].restore_count++; + + /* become new owner */ + + g_cpu_fpu_ctx[this_cpu()].fpu_owner = owner; + owner->xcp.fpu_regs->fpu_trap = 1; +} + +void arm64_fpu_context_restore(void) +{ + struct tcb_s *new_tcb = (struct tcb_s *)arch_get_current_tcb(); + + arm64_fpu_access_trap_enable(); + + if (new_tcb->xcp.fpu_regs->fpu_trap == 0) + { + /* FPU trap hasn't happened at this task */ + + arm64_fpu_access_trap_enable(); + } + else + { + /* FPU trap has happened at this task */ + + if (new_tcb == g_cpu_fpu_ctx[this_cpu()].fpu_owner) + { + arm64_fpu_access_trap_disable(); + } + else + { + arm64_fpu_access_trap_enable(); + } + } + + g_cpu_fpu_ctx[this_cpu()].switch_count++; +} + +void arm64_fpu_enable(void) +{ + irqstate_t flags = up_irq_save(); + + arm64_fpu_access_trap_enable(); + up_irq_restore(flags); +} + +void arm64_fpu_disable(void) +{ + irqstate_t flags = up_irq_save(); + + arm64_fpu_access_trap_disable(); + up_irq_restore(flags); +} + +/*************************************************************************** + * Name: up_fpucmp + * + * Description: + * compare FPU areas from thread context + * + ***************************************************************************/ + +bool up_fpucmp(const void *saveregs1, const void *saveregs2) +{ + const uint64_t *regs1 = saveregs1 + XCPTCONTEXT_GP_SIZE; + const uint64_t *regs2 = saveregs2 + XCPTCONTEXT_GP_SIZE; Review Comment: ```suggestion const uint64_t *regs1 = saveregs1 + XCPTCONTEXT_GP_SIZE; const uint64_t *regs2 = saveregs2 + XCPTCONTEXT_GP_SIZE; ``` ########## arch/arm64/src/common/arm64_fpu.h: ########## @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_fpu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> +#include <debug.h> +#include <assert.h> + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void arm64_init_fpu(struct tcb_s *tcb); +void arm64_destory_fpu(struct tcb_s * tcb); + +void arm64_fpu_disable(void); +void arm64_fpu_enable(void); + +void arm64_fpu_save(struct fpu_reg *saved_fp_context); +void arm64_fpu_restore(struct fpu_reg *saved_fp_context); + +#endif //__ASSEMBLY__ + +#endif /* __ARCH_ARM_SRC_ARMV7_A_ARM_H */ Review Comment: ```suggestion #endif /* __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H */ ``` ########## arch/arm64/src/common/arm64_cpu_psci.h: ########## @@ -0,0 +1,101 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_cpu_psci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__ Review Comment: ```suggestion #ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H #define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H ``` ########## arch/arm64/src/common/arm64_backtrace.c: ########## @@ -0,0 +1,184 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_backtrace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <nuttx/arch.h> + +#include "sched/sched.h" +#include "arm64_internal.h" +#include "arm64_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_FRAME_POINTER) + +/**************************************************************************** + * Name: backtrace + * + * Description: + * backtrace() parsing the return address through frame pointer + * + ****************************************************************************/ + +#ifdef CONFIG_MM_KASAN +__attribute__((no_sanitize_address)) +#endif +static int backtrace(uintptr_t *base, uintptr_t *limit, + uintptr_t *fp, uintptr_t *pc, + void **buffer, int size, int *skip) +{ + int i = 0; + + if (pc) + { + i++; + if (*skip-- <= 0) + { + *buffer++ = pc; + } + } + + for (; i < size; fp = (uintptr_t *)*(fp - 1), i++) + { + if (fp > limit || fp < base || *fp == 0) + { + break; + } + + if (*skip-- <= 0) + { + *buffer++ = (void *)*fp; + } + } + + return i; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_backtrace + * + * Description: + * up_backtrace() returns a backtrace for the TCB, in the array + * pointed to by buffer. A backtrace is the series of currently active + * function calls for the program. Each item in the array pointed to by + * buffer is of type void *, and is the return address from the + * corresponding stack frame. The size argument specifies the maximum + * number of addresses that can be stored in buffer. If the backtrace is + * larger than size, then the addresses corresponding to the size most + * recent function calls are returned; to obtain the complete backtrace, + * make sure that buffer and size are large enough. + * + * Input Parameters: + * tcb - Address of the task's TCB + * buffer - Return address from the corresponding stack frame + * size - Maximum number of addresses that can be stored in buffer + * skip - number of addresses to be skipped + * + * Returned Value: + * up_backtrace() returns the number of addresses returned in buffer + * + ****************************************************************************/ + +#ifdef CONFIG_MM_KASAN +__attribute__((no_sanitize_address)) +#endif +int up_backtrace(struct tcb_s *tcb, + void **buffer, int size, int skip) +{ + struct tcb_s *rtcb = (struct tcb_s *)arch_get_current_tcb(); + struct regs_context * p_regs; + +#if CONFIG_ARCH_INTERRUPTSTACK > 7 + void *istacklimit; +#endif + irqstate_t flags; + int ret; + + if (size <= 0 || !buffer) + { + return 0; + } + + if (tcb == NULL || tcb == rtcb) + { + if (up_interrupt_context()) + { +#if CONFIG_ARCH_INTERRUPTSTACK > 7 +# ifdef CONFIG_SMP + istacklimit = (void *)arm64_intstack_top(); +# else + istacklimit = g_interrupt_stack + INTSTACK_SIZE; +# endif /* CONFIG_SMP */ + ret = backtrace(istacklimit - (CONFIG_ARCH_INTERRUPTSTACK & ~15), + istacklimit, + (void *)__builtin_frame_address(0), + NULL, buffer, size, &skip); +#else + ret = backtrace(rtcb->stack_base_ptr, + rtcb->stack_base_ptr + rtcb->adj_stack_size, + (void *)__builtin_frame_address(0), + NULL, buffer, size, &skip); +#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */ + if (ret < size) + { + p_regs = (struct regs_context *)CURRENT_REGS; + ret += backtrace(rtcb->stack_base_ptr, + rtcb->stack_base_ptr + rtcb->adj_stack_size, + (void *)p_regs->regs[REG_X29], + (void *)p_regs->elr, + &buffer[ret], size - ret, &skip); + } + } + else + { + ret = backtrace(rtcb->stack_base_ptr, + rtcb->stack_base_ptr + rtcb->adj_stack_size, + (void *)__builtin_frame_address(0), + NULL, buffer, size, &skip); + } + } + else + { + flags = enter_critical_section(); + p_regs = (struct regs_context *)CURRENT_REGS; + + ret = backtrace(tcb->stack_base_ptr, + tcb->stack_base_ptr + tcb->adj_stack_size, + (void *)p_regs->regs[REG_X29], + (void *)p_regs->elr, + buffer, size, &skip); + + leave_critical_section(flags); + } + + return ret; +} +#endif /* CONFIG_FRAME_POINTER && !CONFIG_ARM_THUMB */ Review Comment: comment seems to be wrong ########## arch/arm64/src/common/arm64_cache.c: ########## @@ -0,0 +1,449 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_cache.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/cache.h> +#include <nuttx/irq.h> + +#include <nuttx/arch.h> +#include <arch/irq.h> +#include <arch/chip/chip.h> +#include <nuttx/spinlock.h> + +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "arm64_mmu.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* Common operations for the caches + * + * WB means write-back and intends to transfer dirty cache lines to memory in + * a copy-back cache policy. May be a no-op in write-back cache policy. + * + * INVD means invalidate and will mark cache lines as not valid. A future + * access to the associated address is guaranteed to generate a memory fetch. + * + * armv8 data cahce instruction: + * + * DC CIVAC (WB+INVD): + * Data or unified Cache line Clean and Invalidate by VA to PoC + * Clean and Invalidate data cache by address to Point of Coherency. + * + * DC CVAC (WB): + * Data or unified Cache line Clean by VA to PoC + * Clean data cache by address to Point of Coherency. + * + * DC IVAC (INVD): + * Data or unified Cache line Invalidate by VA to PoC + * Invalidate data cache by address to Point of Coherency + */ + +#define CACHE_OP_WB BIT(0) +#define CACHE_OP_INVD BIT(1) +#define CACHE_OP_WB_INVD (CACHE_OP_WB | CACHE_OP_INVD) + +#define LINE_MASK(line) (line - 1) Review Comment: ```suggestion #define LINE_MASK(line) ((line) - 1) ``` ########## arch/arm64/src/common/arm64_arch_timer.h: ########## @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_arch_timer.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__ Review Comment: ```suggestion #ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H #define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H ``` ########## arch/arm64/src/common/arm64_cpu_psci.h: ########## @@ -0,0 +1,101 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_cpu_psci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include <nuttx/config.h> +#include <arch/irq.h> +#include <arch/chip/chip.h> +#include <arch/syscall.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name + +/* PSCI v0.2 interface */ +#define PSCI_0_2_FN_BASE 0x84000000 +#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) +#define PSCI_0_2_64BIT 0x40000000 +#define PSCI_0_2_FN64_BASE \ + (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) + +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) +#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) +#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) +#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) +#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) +#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) +#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) +#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) +#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) + +/* PSCI return values (inclusive of all PSCI versions) */ +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_SUPPORTED -1 +#define PSCI_RET_INVALID_PARAMS -2 +#define PSCI_RET_DENIED -3 +#define PSCI_RET_ALREADY_ON -4 +#define PSCI_RET_ON_PENDING -5 +#define PSCI_RET_INTERNAL_FAILURE -6 +#define PSCI_RET_NOT_PRESENT -7 +#define PSCI_RET_DISABLED -8 +#define PSCI_RET_INVALID_ADDRESS -9 + +/* PSCI version decoding (independent of PSCI version) */ +#define PSCI_VERSION_MAJOR_SHIFT 16 +#define PSCI_VERSION_MINOR_MASK \ + ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) +#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK + +#define PSCI_VERSION_MAJOR(ver) \ + (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) +#define PSCI_VERSION_MINOR(ver) \ + ((ver) & PSCI_VERSION_MINOR_MASK) + +uint32_t psci_version(void); + +typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long, Review Comment: is `*` missing here? ########## arch/arm64/src/common/arm64_arch_timer.h: ########## @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_arch_timer.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include <nuttx/config.h> +#include <arch/irq.h> +#include <arch/chip/chip.h> + +#include "arm64_gic.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CONFIG_ARM_TIMER_SECURE_IRQ (GIC_PPI_INT_BASE + 13) +#define CONFIG_ARM_TIMER_NON_SECURE_IRQ (GIC_PPI_INT_BASE + 14) +#define CONFIG_ARM_TIMER_VIRTUAL_IRQ (GIC_PPI_INT_BASE + 11) +#define CONFIG_ARM_TIMER_HYP_IRQ (GIC_PPI_INT_BASE + 10) + +#define ARM_ARCH_TIMER_IRQ CONFIG_ARM_TIMER_VIRTUAL_IRQ +#define ARM_ARCH_TIMER_PRIO IRQ_DEFAULT_PRIORITY +#define ARM_ARCH_TIMER_FLAGS IRQ_TYPE_LEVEL + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +extern uint64_t arch_counter_read(void); +extern void arch_timer_delay(long mini_sec); +extern void arch_start_timer(void); + +#ifdef CONFIG_SMP +void arm64_smp_timer_init(void); +#endif + +#endif //__ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__ Review Comment: ```suggestion #endif /* __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H */ ``` ########## arch/arm64/src/common/arm64_cpu_psci.h: ########## @@ -0,0 +1,101 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_cpu_psci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include <nuttx/config.h> +#include <arch/irq.h> +#include <arch/chip/chip.h> +#include <arch/syscall.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name + +/* PSCI v0.2 interface */ +#define PSCI_0_2_FN_BASE 0x84000000 +#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) +#define PSCI_0_2_64BIT 0x40000000 +#define PSCI_0_2_FN64_BASE \ + (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) + +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) +#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) +#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) +#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) +#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) +#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) +#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) +#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) +#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) + +/* PSCI return values (inclusive of all PSCI versions) */ +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_SUPPORTED -1 +#define PSCI_RET_INVALID_PARAMS -2 +#define PSCI_RET_DENIED -3 +#define PSCI_RET_ALREADY_ON -4 +#define PSCI_RET_ON_PENDING -5 +#define PSCI_RET_INTERNAL_FAILURE -6 +#define PSCI_RET_NOT_PRESENT -7 +#define PSCI_RET_DISABLED -8 +#define PSCI_RET_INVALID_ADDRESS -9 + +/* PSCI version decoding (independent of PSCI version) */ +#define PSCI_VERSION_MAJOR_SHIFT 16 +#define PSCI_VERSION_MINOR_MASK \ + ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) +#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK + +#define PSCI_VERSION_MAJOR(ver) \ + (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) +#define PSCI_VERSION_MINOR(ver) \ + ((ver) & PSCI_VERSION_MINOR_MASK) + +uint32_t psci_version(void); + +typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long, + unsigned long); + +struct psci_interface +{ + enum arm64_smccc_conduit conduit; + psci_fn *invoke_psci_fn; + uint32_t version; +}; + +int pcsi_cpu_off(void); +int pcsi_cpu_on(unsigned long cpuid, uintptr_t entry_point); + +#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__ */ Review Comment: ```suggestion #endif /* __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H */ ``` ########## arch/arm64/src/common/arm64_fatal.h: ########## @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_fatal.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__ + +/** + * @defgroup fatal_apis Fatal error APIs + * @ingroup kernel_apis + * @{ + */ + +#define K_ERR_CPU_EXCEPTION (0) +#define K_ERR_CPU_MODE32 (1) +#define K_ERR_SPURIOUS_IRQ (2) + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> +#include <debug.h> +#include <assert.h> + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: arm64_fatal_error + * + * Description: + * fatal error handle for arm64 + * Input Parameters: + * reason: error reason + * reg: exception stack reg context + * + * Returned Value: + * + ****************************************************************************/ + +void arm64_fatal_error(unsigned int reason, struct regs_context * reg); +void arm64_dump_fatal(struct regs_context * reg); + +#define __builtin_unreachable() \ + do { \ + sinfo("Unreachable code\n"); \ + PANIC(); \ + } while (true) + +#endif //__ASSEMBLY__ + +#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__ */ Review Comment: ```suggestion #endif /* __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H */ ``` ########## arch/arm64/src/common/arm64_copystate.c: ########## @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_copystate.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <sched.h> +#include <debug.h> +#include <assert.h> +#include <nuttx/arch.h> +#include <nuttx/sched.h> +#include <arch/syscall.h> +#include <arch/irq.h> + +#include "arm64_internal.h" + +#ifdef CONFIG_ARCH_FPU +#include "arm64_fpu.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +int arch_save_fpucontext(void *saveregs) +{ + irqstate_t flags; + uint64_t * p_save; Review Comment: ```suggestion uint64_t *p_save; ``` ########## arch/arm64/src/common/arm64_fpu.h: ########## @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_fpu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__ Review Comment: ```suggestion #ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H #define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H ``` ########## arch/arm64/src/common/arm64_gic.h: ########## @@ -0,0 +1,317 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_gic.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include <nuttx/config.h> +#include <arch/irq.h> +#include <arch/chip/chip.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GIC Distributor register Interface Base Addresses + * Arm® Generic Interrupt Controller Architecture Specification + * GIC architecture version 3 and version 4 + */ + +#define GIC_DIST_BASE CONFIG_GICD_BASE +#define GICD_CTLR (GIC_DIST_BASE + 0x0) +#define GICD_TYPER (GIC_DIST_BASE + 0x4) +#define GICD_IIDR (GIC_DIST_BASE + 0x8) +#define GICD_STATUSR (GIC_DIST_BASE + 0x10) +#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40) +#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48) +#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50) +#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58) +#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80) +#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100) +#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180) +#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200) +#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280) +#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300) +#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380) +#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400) +#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800) +#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00) +#define GICD_SGIR (GIC_DIST_BASE + 0xf00) +#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0) +#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8) + +/* Offsets from GICD base or GICR(n) SGI_base */ +#define GIC_DIST_IGROUPR 0x0080 +#define GIC_DIST_ISENABLER 0x0100 +#define GIC_DIST_ICENABLER 0x0180 +#define GIC_DIST_ISPENDR 0x0200 +#define GIC_DIST_ICPENDR 0x0280 +#define GIC_DIST_ISACTIVER 0x0300 +#define GIC_DIST_ICACTIVER 0x0380 +#define GIC_DIST_IPRIORITYR 0x0400 +#define GIC_DIST_ITARGETSR 0x0800 +#define GIC_DIST_ICFGR 0x0c00 +#define GIC_DIST_IGROUPMODR 0x0d00 +#define GIC_DIST_SGIR 0x0f00 + +/* GICD GICR common access macros */ + +#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4) +#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4) +#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4) +#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4) +#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4) +#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n) +#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4) +#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4) +#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4) + +/* GICD_PIDR2 : Peripheral ID2 Register + * bit assignments + * [31:8] - IMPLEMENTATION DEFINED + * [7:4] ArchRev 0x1. GICv1. + * 0x2. GICv2. + * 0x3. GICv3. + * 0x4. GICv4. + * [3:0] - IMPLEMENTATION DEFINED. + */ +#define GICD_PIDR2_ARCH_MASK 0xf0 +#define GICD_PIDR2_ARCH_GICV3 0x30 +#define GICD_PIDR2_ARCH_GICV4 0x40 + +/* GICD_TYPER : Interrupt Controller Type Register + * Arm® Generic Interrupt Controller Architecture Specification + * GIC architecture version 3 and version 4 + */ +#define GICD_TYPER_RSS (1U << 26) +#define GICD_TYPER_LPIS (1U << 17) +#define GICD_TYPER_MBIS (1U << 16) +#define GICD_TYPER_ESPI (1U << 8) +#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) +#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) +#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) +#define GICD_TYPER_ESPIS(typer) \ + (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) + +/* Common Helper Constants */ +#define GIC_SGI_INT_BASE 0 +#define GIC_PPI_INT_BASE 16 +#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \ + ((intid) < GIC_PPI_INT_BASE)) + +#define GIC_SPI_INT_BASE 32 +#define GIC_NUM_INTR_PER_REG 32 +#define GIC_NUM_CFG_PER_REG 16 +#define GIC_NUM_PRI_PER_REG 4 + +/* GIC idle priority : value '0xff' will allow all interrupts */ + +#define GIC_IDLE_PRIO 0xff + +/* Priority levels 0:255 */ + +#define GIC_PRI_MASK 0xff + +/* '0xa0'is used to initialize each interrtupt default priority. + * This is an arbitrary value in current context. + * Any value '0x80' to '0xff' will work for both NS and S state. + * The values of individual interrupt and default has to be chosen + * carefully if PMR and BPR based nesting and preemption has to be done. + */ + +#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0 + +/* Register bit definitions */ + +/* GICD_CTLR Interrupt group definitions */ +#define GICD_CTLR_ENABLE_G0 0 +#define GICD_CTLR_ENABLE_G1NS 1 +#define GICD_CTLR_ENABLE_G1S 2 +#define GICD_CTRL_ARE_S 4 +#define GICD_CTRL_ARE_NS 5 +#define GICD_CTRL_NS 6 +#define GICD_CGRL_E1NWF 7 + +/* GICD_CTLR Register write progress bit */ +#define GICD_CTLR_RWP 31 + +/* GICR_CTLR */ +#define GICR_CTLR_ENABLE_LPIS BIT(0) +#define GICR_CTLR_RWP 3 + +/* GICD_TYPER.ITLinesNumber 0:4 */ +#define GICD_TYPER_ITLINESNUM_MASK 0x1f + +/* GICR： Re-Distributor registers, offsets from RD_base(n) */ +#define GICR_CTLR 0x0000 +#define GICR_IIDR 0x0004 +#define GICR_TYPER 0x0008 +#define GICR_STATUSR 0x0010 +#define GICR_WAKER 0x0014 +#define GICR_SETLPIR 0x0040 +#define GICR_CLRLPIR 0x0048 +#define GICR_PROPBASER 0x0070 +#define GICR_PENDBASER 0x0078 +#define GICR_INVLPIR 0x00A0 +#define GICR_INVALLR 0x00B0 +#define GICR_SYNCR 0x00C0 +#define GICR_MOVLPIR 0x0100 +#define GICR_MOVALLR 0x0110 +#define GICR_IDREGS 0xFFD0 +#define GICR_PIDR2 0xFFE8 + +/* GICR_PIDR2 : Peripheral ID2 Register + * bit assignments are the same as those for GICD_PIDR2) + * [31:8] - IMPLEMENTATION DEFINED + * [7:4] ArchRev 0x1. GICv1. + * 0x2. GICv2. + * 0x3. GICv3. + * 0x4. GICv4. + * [3:0] - IMPLEMENTATION DEFINED. + */ + +#define GICR_PIDR2_ARCH_MASK 0xf0 +#define GICR_PIDR2_ARCH_GICV3 0x30 +#define GICR_PIDR2_ARCH_GICV4 0x40 + +/* GICR_TYPER : Redistributor Type Register + * Arm® Generic Interrupt Controller Architecture Specification + * GIC architecture version 3 and version 4 + * chapter 9.11.35 for detail descriptions + */ + +#define GICR_TYPER_PLPIS (1U << 0) +#define GICR_TYPER_VLPIS (1U << 1) +#define GICR_TYPER_DIRECTLPIS (1U << 3) +#define GICR_TYPER_LAST (1U << 4) + +/* GICR_WAKER */ +#define GICR_WAKER_PS 1 +#define GICR_WAKER_CA 2 + +/* SGI base is at 64K offset from Redistributor */ +#define GICR_SGI_BASE_OFF 0x10000 + +/* GICD_ICFGR */ +#define GICD_ICFGR_MASK BIT_MASK(2) +#define GICD_ICFGR_TYPE BIT(1) + +/* BIT(0) reserved for IRQ_ZERO_LATENCY */ +#define IRQ_TYPE_LEVEL BIT(1) +#define IRQ_TYPE_EDGE BIT(2) + +#define GIC_SPI_INT_BASE 32 +#define GIC_SPI_MAX_INTID 1019 +#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && \ + ((intid) <= GIC_SPI_MAX_INTID)) + +/* GITCD_IROUTER */ +#define GIC_DIST_IROUTER 0x6000 +#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8) + +/* BIT(0) reserved for IRQ_ZERO_LATENCY */ +#define IRQ_TYPE_LEVEL BIT(1) +#define IRQ_TYPE_EDGE BIT(2) + +#define IRQ_DEFAULT_PRIORITY 0xa0 + +#define GIC_IRQ_SGI0 0 +#define GIC_IRQ_SGI1 1 +#define GIC_IRQ_SGI2 2 +#define GIC_IRQ_SGI3 3 +#define GIC_IRQ_SGI4 4 +#define GIC_IRQ_SGI5 5 +#define GIC_IRQ_SGI6 6 +#define GIC_IRQ_SGI7 7 +#define GIC_IRQ_SGI8 8 +#define GIC_IRQ_SGI9 9 +#define GIC_IRQ_SGI10 10 +#define GIC_IRQ_SGI11 11 +#define GIC_IRQ_SGI12 12 +#define GIC_IRQ_SGI13 13 +#define GIC_IRQ_SGI14 14 +#define GIC_IRQ_SGI15 15 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +bool arm64_gic_irq_is_enabled(unsigned int intid); +int arm64_gic_initialize(void); +void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio, + uint32_t flags); + +/**************************************************************************** + * Name: arm64_decodeirq + * + * Description: + * This function is called from the IRQ vector handler in arm_vectors.S. + * At this point, the interrupt has been taken and the registers have + * been saved on the stack. This function simply needs to determine the + * the irq number of the interrupt and then to call arm_doirq to dispatch + * the interrupt. + * + * Input Parameters: + * regs - A pointer to the register save area on the stack. + * + ****************************************************************************/ + +uint64_t * arm64_decodeirq(uint64_t * regs); + +int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, + uint16_t target_list); + +#ifdef CONFIG_SMP + +#define SGI_CPU_PAUSE GIC_IRQ_SGI0 + +/**************************************************************************** + * Name: arm64_pause_handler + * + * Description: + * This is the handler for SGI2. It performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * Standard interrupt handling + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int arm64_pause_handler(int irq, void *context, void *arg); + +void arm64_gic_secondary_init(void); + +int arm64_smp_sgi_init(void); + +#endif + +#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__ */ Review Comment: ```suggestion #endif /* __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H */ ``` ########## arch/arm64/src/common/arm64_gic.h: ########## @@ -0,0 +1,317 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_gic.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__ Review Comment: ```suggestion #ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H #define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H ``` ########## arch/arm64/src/common/arm64_fatal.h: ########## @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_fatal.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__ +#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__ Review Comment: ```suggestion #ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H #define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H ``` ########## arch/arm64/include/irq.h: ########## @@ -0,0 +1,438 @@ +/**************************************************************************** + * arch/arm64/include/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM64_INCLUDE_IRQ_H +#define __ARCH_ARM64_INCLUDE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include NuttX-specific IRQ definitions */ + +#include <nuttx/irq.h> + +/* Include chip-specific IRQ definitions (including IRQ numbers) */ + +#include <arch/chip/irq.h> + +#include <nuttx/config.h> + +#ifndef __ASSEMBLY__ +# include <stdint.h> +# include <arch/arch.h> +#endif + +/**************************************************************************** + * Exception stack frame format: + * + * x0 ~ x18, x30 (lr), spsr and elr + * Corruptible Registers and exception context + * reference to Armv8-A Instruction Set Architecture + * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS + * need to be saved in all exception + * + * x19 ~ x29, sp_el0, sp_elx + * Callee-saved Registers and SP pointer + * reference to Armv8-A Instruction Set Architecture + * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS + * These registers frame is allocated on stack frame + * when a exception is occurred and saved at task switch + * or crash exception + * check arm64_vectors.S for detail + * + ****************************************************************************/ + +/**************************************************************************** + * Registers and exception context + * Note: + * REG_EXEC_DEPTH indicate the task's exception depth + * + ****************************************************************************/ + +#define REG_X0 (0) +#define REG_X1 (1) +#define REG_X2 (2) +#define REG_X3 (3) +#define REG_X4 (4) +#define REG_X5 (5) +#define REG_X6 (6) +#define REG_X7 (7) +#define REG_X8 (8) +#define REG_X9 (9) +#define REG_X10 (10) +#define REG_X11 (11) +#define REG_X12 (12) +#define REG_X13 (13) +#define REG_X14 (14) +#define REG_X15 (15) +#define REG_X16 (16) +#define REG_X17 (17) +#define REG_X18 (18) +#define REG_X19 (19) +#define REG_X20 (20) +#define REG_X21 (21) +#define REG_X22 (22) +#define REG_X23 (23) +#define REG_X24 (24) +#define REG_X25 (25) +#define REG_X26 (26) +#define REG_X27 (27) +#define REG_X28 (28) +#define REG_X29 (29) +#define REG_X30 (30) +#define REG_SP_ELX (31) +#define REG_ELR (32) +#define REG_SPSR (33) +#define REG_SP_EL0 (34) +#define REG_EXE_DEPTH (35) +#define REG_TPIDR_EL0 (36) +#define REG_TPIDR_EL1 (37) + +/* In Armv8-A Architecture, the stack must align with 16 byte */ + +#define XCPTCONTEXT_GP_REGS (38) +#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS) + +#ifdef CONFIG_ARCH_FPU + +/**************************************************************************** + * q0 ~ q31(128bit), fpsr, fpcr + * armv8 fpu registers and context + * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context + * is allocated on stack frame at exception and store/restore + * when switching FPU context + * check arm64_fpu.c for detail + * + ****************************************************************************/ + +/* 128bit registers */ + +#define FPU_REG_Q0 (0) +#define FPU_REG_Q1 (1) +#define FPU_REG_Q2 (2) +#define FPU_REG_Q3 (3) +#define FPU_REG_Q4 (4) +#define FPU_REG_Q5 (5) +#define FPU_REG_Q6 (6) +#define FPU_REG_Q7 (7) +#define FPU_REG_Q8 (8) +#define FPU_REG_Q9 (9) +#define FPU_REG_Q10 (10) +#define FPU_REG_Q11 (11) +#define FPU_REG_Q12 (12) +#define FPU_REG_Q13 (13) +#define FPU_REG_Q14 (14) +#define FPU_REG_Q15 (15) +#define FPU_REG_Q16 (16) +#define FPU_REG_Q17 (17) +#define FPU_REG_Q18 (18) +#define FPU_REG_Q19 (19) +#define FPU_REG_Q20 (20) +#define FPU_REG_Q21 (21) +#define FPU_REG_Q22 (22) +#define FPU_REG_Q23 (23) +#define FPU_REG_Q24 (24) +#define FPU_REG_Q25 (25) +#define FPU_REG_Q26 (26) +#define FPU_REG_Q27 (27) +#define FPU_REG_Q28 (28) +#define FPU_REG_Q29 (29) +#define FPU_REG_Q30 (30) +#define FPU_REG_Q31 (31) + +/* 32 bit registers + */ +#define FPU_REG_FPSR (0) +#define FPU_REG_FPCR (1) + +/* FPU registers(Q0~Q31, 128bit): 32x2 = 64 + * FPU FPSR/SPSR(32 bit) : 1 + * FPU TRAP: 1 + * 64 + 1 + 1 = 66 + */ +#define ARM64_FPU_REGS (66) +#else +#define ARM64_FPU_REGS (0) Review Comment: ```suggestion #define ARM64_FPU_REGS (66) #else #define ARM64_FPU_REGS (0) ``` -- This is an automated message from the Apache Git Service. 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