onegray commented on code in PR #6426: URL: https://github.com/apache/incubator-nuttx/pull/6426#discussion_r896523732
########## arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h: ########## @@ -131,174 +129,174 @@ /* Register Addresses *******************************************************/ -#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) -#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) -#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) -#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) -#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) -#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) -#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) -#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) -#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) -#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) -#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) -#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) -#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) -#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) -#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) -#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) -#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) -#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) -#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) -#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) +#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) +#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) +#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) +#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) +#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) +#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) +#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) +#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) +#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) +#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) +#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) +#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) +#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) +#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) +#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) +#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) +#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) +#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) +#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) +#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ /* Flash Access Control Register (ACR) */ -#define FLASH_ACR_LATENCY_SHIFT (0) -#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) -# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */ -# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ -# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ -# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ - -#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */ -#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ -#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ -#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ -#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ -#define FLASH_ACR_PES (1 << 15) /* Bit 15: Suspend flash program */ -#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Is user flash empty */ +#define FLASH_ACR_LATENCY_SHIFT (0) +#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ + +#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */ +#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ +#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ +#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ +#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ +#define FLASH_ACR_PES (1 << 15) /* Bit 15: Suspend flash program */ +#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Is user flash empty */ /* Flash Access Control Register 2 (ACR2) */ -#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash priviliged access mode */ -#define FLASH_ACR2_HDPADIS (1 << 1) /* Bit 1: Disable user flash hide protection area access */ -#define FLASH_ACR2_C2SWDBGEN (1 << 2) /* Bit 2: Enable cpu2 debug access */ +#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash priviliged access mode */ +#define FLASH_ACR2_HDPADIS (1 << 1) /* Bit 1: Disable user flash hide protection area access */ +#define FLASH_ACR2_C2SWDBGEN (1 << 2) /* Bit 2: Enable cpu2 debug access */ /* Flash Status Register (SR) */ -#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ -#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ -#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ -#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ -#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ -#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ -#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ -#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */ -#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ -#define FLASH_SR_OPTNV (1 << 13) /* Bit 13: User option OPTVAL indication */ -#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ -#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ -#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ -#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */ -#define FLASH_SR_PESD (1 << 19) /* Bit 19: Program or erase operation suspended */ +#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ +#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ +#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */ +#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ +#define FLASH_SR_OPTNV (1 << 13) /* Bit 13: User option OPTVAL indication */ +#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ +#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ +#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ +#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */ +#define FLASH_SR_PESD (1 << 19) /* Bit 19: Program or erase operation suspended */ /* Flash Control Register (CR) */ -#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */ -#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */ -#define FLASH_CR_MER (1 << 2) /* Bit 2 : Mass Erase */ +#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */ +#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */ +#define FLASH_CR_MER (1 << 2) /* Bit 2 : Mass Erase */ -#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */ -#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT) -#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n, n=0..127 */ +#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */ +#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT) +#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n, n=0..127 */ -#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */ -#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */ -#define FLASH_CR_FSTPG (1 << 23) /* Bit 23: Fast programming */ -#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ -#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ -#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */ -#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */ -#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */ -#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ +#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */ +#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */ +#define FLASH_CR_FSTPG (1 << 23) /* Bit 23: Fast programming */ Review Comment: ```suggestion #define FLASH_CR_FSTPG (1 << 18) /* Bit 18: Fast programming */ ``` ########## arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h: ########## @@ -131,174 +129,174 @@ /* Register Addresses *******************************************************/ -#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) Review Comment: which style is preferred, with or without spaces around "+" ? ########## arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h: ########## @@ -131,174 +129,174 @@ /* Register Addresses *******************************************************/ -#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) -#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) -#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) -#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) -#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) -#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) -#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) -#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) -#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) -#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) -#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) -#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) -#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) -#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) -#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) -#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) -#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) -#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) -#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) -#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) +#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) +#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) +#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) +#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) +#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) +#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) +#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) +#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) +#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) +#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) +#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) +#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) +#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) +#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) +#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) +#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) +#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) +#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) +#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) +#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ /* Flash Access Control Register (ACR) */ -#define FLASH_ACR_LATENCY_SHIFT (0) -#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) -# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */ -# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ -# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ -# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ - -#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */ -#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ -#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ -#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ -#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ -#define FLASH_ACR_PES (1 << 15) /* Bit 15: Suspend flash program */ -#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Is user flash empty */ +#define FLASH_ACR_LATENCY_SHIFT (0) +#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ + +#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */ +#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ +#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ +#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ +#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ +#define FLASH_ACR_PES (1 << 15) /* Bit 15: Suspend flash program */ +#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Is user flash empty */ /* Flash Access Control Register 2 (ACR2) */ -#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash priviliged access mode */ -#define FLASH_ACR2_HDPADIS (1 << 1) /* Bit 1: Disable user flash hide protection area access */ -#define FLASH_ACR2_C2SWDBGEN (1 << 2) /* Bit 2: Enable cpu2 debug access */ +#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash priviliged access mode */ +#define FLASH_ACR2_HDPADIS (1 << 1) /* Bit 1: Disable user flash hide protection area access */ +#define FLASH_ACR2_C2SWDBGEN (1 << 2) /* Bit 2: Enable cpu2 debug access */ /* Flash Status Register (SR) */ -#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ -#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ -#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ -#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ -#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ -#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ -#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ -#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */ -#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ -#define FLASH_SR_OPTNV (1 << 13) /* Bit 13: User option OPTVAL indication */ -#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ -#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ -#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ -#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */ -#define FLASH_SR_PESD (1 << 19) /* Bit 19: Program or erase operation suspended */ +#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ +#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ +#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */ +#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ +#define FLASH_SR_OPTNV (1 << 13) /* Bit 13: User option OPTVAL indication */ +#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ +#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ +#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ +#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */ +#define FLASH_SR_PESD (1 << 19) /* Bit 19: Program or erase operation suspended */ /* Flash Control Register (CR) */ -#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */ -#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */ -#define FLASH_CR_MER (1 << 2) /* Bit 2 : Mass Erase */ +#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */ +#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */ +#define FLASH_CR_MER (1 << 2) /* Bit 2 : Mass Erase */ -#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */ -#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT) -#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n, n=0..127 */ +#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */ +#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT) +#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n, n=0..127 */ -#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */ -#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */ -#define FLASH_CR_FSTPG (1 << 23) /* Bit 23: Fast programming */ -#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ -#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ -#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */ -#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */ -#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */ -#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ +#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */ +#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */ +#define FLASH_CR_FSTPG (1 << 23) /* Bit 23: Fast programming */ +#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ +#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ +#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */ +#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */ +#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */ +#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ /* Flash ECC Register (ECCR) */ -#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-15: Read protect */ -# define FLASH_ECCR_ADDR_ECC_MASK (0xffff << FLASH_ECCR_ADDR_ECC_SHIFT) -#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */ -#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */ -#define FLASH_ECCR_CPUID_SHIFT (26) -# define FLASH_ECCR_CPUID_MASK (0x7 << FLASH_ECCR_CPUID_SHIFT) -# define FLASH_ECCR_CPUID_CPU1 (0x0 << FLASH_ECCR_CPUID_SHIFT) /* 000: cpu1 access caused ECC failure */ -# define FLASH_ECCR_CPUID_CPU2 (0x1 << FLASH_ECCR_CPUID_SHIFT) /* 001: cpu2 access caused ECC failure */ +#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-15: Read protect */ Review Comment: ```suggestion #define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-16: ECC fail address */ ``` ########## arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h: ########## @@ -131,174 +129,174 @@ /* Register Addresses *******************************************************/ -#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) -#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) -#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) -#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) -#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) -#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) -#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) -#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) -#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) -#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) -#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) -#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) -#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) -#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) -#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) -#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) -#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) -#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) -#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) -#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) +#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) +#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) +#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) +#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) +#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) +#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) +#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) +#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) +#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) +#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) +#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) +#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) +#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) +#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) +#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) +#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) +#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) +#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) +#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) +#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ /* Flash Access Control Register (ACR) */ -#define FLASH_ACR_LATENCY_SHIFT (0) -#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) -# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */ -# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ -# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ -# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ - -#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */ -#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ -#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ -#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ -#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ -#define FLASH_ACR_PES (1 << 15) /* Bit 15: Suspend flash program */ -#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Is user flash empty */ +#define FLASH_ACR_LATENCY_SHIFT (0) +#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ + +#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */ +#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ +#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ +#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ +#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ +#define FLASH_ACR_PES (1 << 15) /* Bit 15: Suspend flash program */ +#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Is user flash empty */ /* Flash Access Control Register 2 (ACR2) */ -#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash priviliged access mode */ -#define FLASH_ACR2_HDPADIS (1 << 1) /* Bit 1: Disable user flash hide protection area access */ -#define FLASH_ACR2_C2SWDBGEN (1 << 2) /* Bit 2: Enable cpu2 debug access */ +#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash priviliged access mode */ +#define FLASH_ACR2_HDPADIS (1 << 1) /* Bit 1: Disable user flash hide protection area access */ +#define FLASH_ACR2_C2SWDBGEN (1 << 2) /* Bit 2: Enable cpu2 debug access */ /* Flash Status Register (SR) */ -#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ -#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ -#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ -#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ -#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ -#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ -#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ -#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */ -#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ -#define FLASH_SR_OPTNV (1 << 13) /* Bit 13: User option OPTVAL indication */ -#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ -#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ -#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ -#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */ -#define FLASH_SR_PESD (1 << 19) /* Bit 19: Program or erase operation suspended */ +#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ +#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ +#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */ +#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ +#define FLASH_SR_OPTNV (1 << 13) /* Bit 13: User option OPTVAL indication */ +#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ +#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ +#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ +#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */ +#define FLASH_SR_PESD (1 << 19) /* Bit 19: Program or erase operation suspended */ /* Flash Control Register (CR) */ -#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */ -#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */ -#define FLASH_CR_MER (1 << 2) /* Bit 2 : Mass Erase */ +#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */ +#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */ +#define FLASH_CR_MER (1 << 2) /* Bit 2 : Mass Erase */ -#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */ -#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT) -#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n, n=0..127 */ +#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */ +#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT) +#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n, n=0..127 */ -#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */ -#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */ -#define FLASH_CR_FSTPG (1 << 23) /* Bit 23: Fast programming */ -#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ -#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ -#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */ -#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */ -#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */ -#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ +#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */ +#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */ +#define FLASH_CR_FSTPG (1 << 23) /* Bit 23: Fast programming */ +#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ +#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ +#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */ +#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */ +#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */ +#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ /* Flash ECC Register (ECCR) */ -#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-15: Read protect */ -# define FLASH_ECCR_ADDR_ECC_MASK (0xffff << FLASH_ECCR_ADDR_ECC_SHIFT) -#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */ -#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */ -#define FLASH_ECCR_CPUID_SHIFT (26) -# define FLASH_ECCR_CPUID_MASK (0x7 << FLASH_ECCR_CPUID_SHIFT) -# define FLASH_ECCR_CPUID_CPU1 (0x0 << FLASH_ECCR_CPUID_SHIFT) /* 000: cpu1 access caused ECC failure */ -# define FLASH_ECCR_CPUID_CPU2 (0x1 << FLASH_ECCR_CPUID_SHIFT) /* 001: cpu2 access caused ECC failure */ +#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-15: Read protect */ +# define FLASH_ECCR_ADDR_ECC_MASK (0xffff << FLASH_ECCR_ADDR_ECC_SHIFT) Review Comment: ```suggestion # define FLASH_ECCR_ADDR_ECC_MASK (0x1ffff << FLASH_ECCR_ADDR_ECC_SHIFT) ``` -- This is an automated message from the Apache Git Service. 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