This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 9d9d591b93 arch/risc-v: Unify common source include
9d9d591b93 is described below
commit 9d9d591b935ff00eba21473dbd52cdab4424342b
Author: Huang Qi <huang...@xiaomi.com>
AuthorDate: Mon May 30 16:48:29 2022 +0800
arch/risc-v: Unify common source include
Signed-off-by: Huang Qi <huang...@xiaomi.com>
---
arch/risc-v/src/bl602/Make.defs | 35 +-----------
arch/risc-v/src/c906/Make.defs | 39 +------------
arch/risc-v/src/{qemu-rv => common}/Make.defs | 42 +++++---------
arch/risc-v/src/esp32c3/Make.defs | 34 +-----------
arch/risc-v/src/fe310/Make.defs | 29 +---------
arch/risc-v/src/k210/Make.defs | 44 +--------------
arch/risc-v/src/litex/Make.defs | 29 +---------
arch/risc-v/src/mpfs/Make.defs | 65 +---------------------
arch/risc-v/src/qemu-rv/Make.defs | 79 +--------------------------
arch/risc-v/src/rv32m1/Make.defs | 28 +---------
10 files changed, 33 insertions(+), 391 deletions(-)
diff --git a/arch/risc-v/src/bl602/Make.defs b/arch/risc-v/src/bl602/Make.defs
index 1b6fbe76e4..6aebdda9e3 100644
--- a/arch/risc-v/src/bl602/Make.defs
+++ b/arch/risc-v/src/bl602/Make.defs
@@ -18,43 +18,12 @@
#
############################################################################
+include common/Make.defs
+
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = bl602_head.S
-# Specify our general Assembly files
-CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
-
-# Specify C code within the common directory to be included
-CMN_CSRCS += riscv_initialize.c riscv_swint.c
-CMN_CSRCS += riscv_createstack.c riscv_exit.c
-CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
-CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
-CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
-CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c
riscv_usestack.c
-CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_getnewintctx.c riscv_doirq.c
-CMN_CSRCS += riscv_exception.c riscv_mtimer.c riscv_misaligned.c
-CMN_CSRCS += riscv_saveusercontext.c
-
-ifeq ($(CONFIG_SCHED_BACKTRACE),y)
-CMN_CSRCS += riscv_backtrace.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += riscv_checkstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_FPU),y)
-CMN_ASRCS += riscv_fpu.S
-CMN_CSRCS += riscv_fpucmp.c
-endif
-
-ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_ASRCS += vfork.S
-CMN_CSRCS += riscv_vfork.c
-endif
-
# Specify our C code within this directory to be included
CHIP_CSRCS = bl602_allocateheap.c
CHIP_CSRCS += bl602_irq.c bl602_irq_dispatch.c
diff --git a/arch/risc-v/src/c906/Make.defs b/arch/risc-v/src/c906/Make.defs
index 779a96c74b..79173d159c 100644
--- a/arch/risc-v/src/c906/Make.defs
+++ b/arch/risc-v/src/c906/Make.defs
@@ -18,43 +18,12 @@
#
############################################################################
+include common/Make.defs
+
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = c906_head.S
-# Specify our general Assembly files
-CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
-
-# Specify C code within the common directory to be included
-CMN_CSRCS += riscv_initialize.c riscv_swint.c
-CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_exception.c
-CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
-CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
-CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
-CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
-CMN_CSRCS += riscv_mdelay.c riscv_idle.c riscv_doirq.c riscv_mtimer.c
-CMN_CSRCS += riscv_tcbinfo.c riscv_getnewintctx.c
-CMN_CSRCS += riscv_saveusercontext.c
-
-ifeq ($(CONFIG_SCHED_BACKTRACE),y)
-CMN_CSRCS += riscv_backtrace.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += riscv_checkstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_FPU),y)
-CMN_ASRCS += riscv_fpu.S
-CMN_CSRCS += riscv_fpucmp.c
-endif
-
-ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_ASRCS += vfork.S
-CMN_CSRCS += riscv_vfork.c
-endif
-
# Specify our C code within this directory to be included
CHIP_CSRCS = c906_allocateheap.c c906_clockconfig.c
CHIP_CSRCS += c906_irq.c c906_irq_dispatch.c
@@ -62,9 +31,5 @@ CHIP_CSRCS += c906_lowputc.c c906_serial.c
CHIP_CSRCS += c906_start.c c906_timerisr.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += riscv_task_start.c riscv_pthread_start.c
-CMN_CSRCS += riscv_signal_dispatch.c riscv_pmp.c
-CMN_UASRCS += riscv_signal_handler.S
-
CHIP_CSRCS += c906_userspace.c
endif
diff --git a/arch/risc-v/src/qemu-rv/Make.defs
b/arch/risc-v/src/common/Make.defs
similarity index 78%
copy from arch/risc-v/src/qemu-rv/Make.defs
copy to arch/risc-v/src/common/Make.defs
index 7fb8ae50e4..f431b3fc1f 100644
--- a/arch/risc-v/src/qemu-rv/Make.defs
+++ b/arch/risc-v/src/common/Make.defs
@@ -1,5 +1,5 @@
############################################################################
-# arch/risc-v/src/qemu-rv/Make.defs
+# nuttx/arch/risc-v/src/common/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
@@ -18,22 +18,18 @@
#
############################################################################
-# Specify our HEAD assembly file. This will be linked as
-# the first object file, so it will appear at address 0
-HEAD_ASRC = qemu_rv_head.S
-
ifeq ($(CONFIG_BUILD_KERNEL),y)
STARTUP_OBJS = crt0$(OBJEXT)
endif
# Specify our general Assembly files
-CMN_ASRCS += riscv_vectors.S riscv_exception_common.S
+CMN_ASRCS += riscv_vectors.S riscv_exception_common.S riscv_mhartid.S
# Specify C code within the common directory to be included
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
+CMN_CSRCS += riscv_modifyreg32.c riscv_mdelay.c riscv_puts.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
@@ -41,9 +37,19 @@ CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c
riscv_cpuidlestack.c
CMN_CSRCS += riscv_exception.c riscv_getnewintctx.c riscv_doirq.c
CMN_CSRCS += riscv_saveusercontext.c
-ifeq ($(CONFIG_SMP), y)
+ifeq ($(CONFIG_SMP),y)
CMN_CSRCS += riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c
-CMN_ASRCS += riscv_mhartid.S
+endif
+
+ifeq ($(CONFIG_RISCV_MISALIGNED_HANDLER),y)
+CMN_CSRCS += riscv_misaligned.c
+endif
+
+ifneq ($(CONFIG_BUILD_FLAT),y)
+CMN_CSRCS += riscv_task_start.c
+CMN_CSRCS += riscv_pthread_start.c
+CMN_CSRCS += riscv_signal_dispatch.c
+CMN_UASRCS += riscv_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
@@ -77,20 +83,6 @@ CMN_ASRCS += riscv_semihost.S
CMN_CSRCS += riscv_hostfs.c
endif
-# Specify our C code within this directory to be included
-CHIP_CSRCS = qemu_rv_start.c qemu_rv_irq_dispatch.c qemu_rv_irq.c
-CHIP_CSRCS += qemu_rv_timerisr.c qemu_rv_allocateheap.c
-
-ifeq ($(CONFIG_BUILD_KERNEL),y)
-CHIP_CSRCS += qemu_rv_mm_init.c
-endif
-
-ifneq ($(CONFIG_BUILD_FLAT),y)
-CMN_CSRCS += riscv_task_start.c
-CMN_CSRCS += riscv_pthread_start.c
-CMN_CSRCS += riscv_signal_dispatch.c
-endif
-
ifeq ($(CONFIG_ARCH_USE_MPU),y)
CMN_CSRCS += riscv_pmp.c
endif
@@ -106,7 +98,3 @@ endif
ifeq ($(CONFIG_ARCH_ADDRENV),y)
CMN_CSRCS += riscv_addrenv.c riscv_pgalloc.c riscv_addrenv_perms.c
endif
-
-ifeq ($(CONFIG_MM_PGALLOC),y)
-CHIP_CSRCS += qemu_rv_pgalloc.c
-endif
diff --git a/arch/risc-v/src/esp32c3/Make.defs
b/arch/risc-v/src/esp32c3/Make.defs
index d25da5cb20..fcf0ada929 100644
--- a/arch/risc-v/src/esp32c3/Make.defs
+++ b/arch/risc-v/src/esp32c3/Make.defs
@@ -19,6 +19,7 @@
############################################################################
include chip/Bootloader.mk
+include common/Make.defs
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
@@ -29,36 +30,7 @@ CHIP_ASRCS = esp32c3_vectors.S
# Specify our general Assembly files
-CMN_ASRCS = riscv_exception_common.S
-
-# Specify C code within the common directory to be included
-
-CMN_CSRCS += riscv_initialize.c riscv_swint.c
-CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
riscv_exception.c
-CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
-CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
-CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
-CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c
riscv_usestack.c
-CMN_CSRCS += riscv_tcbinfo.c riscv_getnewintctx.c riscv_doirq.c
-CMN_CSRCS += riscv_saveusercontext.c
-
-ifeq ($(CONFIG_SCHED_BACKTRACE),y)
-CMN_CSRCS += riscv_backtrace.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += riscv_checkstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_ASRCS += vfork.S
-CMN_CSRCS += riscv_vfork.c
-endif
-
-ifeq ($(CONFIG_ARCH_USE_MPU),y)
-CMN_CSRCS += riscv_pmp.c
-endif
+CMN_ASRCS := $(filter-out riscv_vectors.S,$(CMN_ASRCS))
# Specify our C code within this directory to be included
@@ -71,8 +43,6 @@ CHIP_CSRCS += esp32c3_uid.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += esp32c3_userspace.c
-CMN_UASRCS += riscv_signal_handler.S
-CMN_CSRCS += riscv_task_start.c riscv_pthread_start.c riscv_signal_dispatch.c
endif
ifeq ($(CONFIG_SCHED_TICKLESS),y)
diff --git a/arch/risc-v/src/fe310/Make.defs b/arch/risc-v/src/fe310/Make.defs
index bf49b2d0f5..ecdb142812 100644
--- a/arch/risc-v/src/fe310/Make.defs
+++ b/arch/risc-v/src/fe310/Make.defs
@@ -18,37 +18,12 @@
#
############################################################################
+include common/Make.defs
+
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = fe310_head.S
-# Specify our general Assembly files
-CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
-
-# Specify C code within the common directory to be included
-CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_exception.c riscv_mtimer.c
-CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
-CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
-CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
-CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
-CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c
riscv_usestack.c
-CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_getnewintctx.c riscv_doirq.c
-CMN_CSRCS += riscv_saveusercontext.c
-
-ifeq ($(CONFIG_SCHED_BACKTRACE),y)
-CMN_CSRCS += riscv_backtrace.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += riscv_checkstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_ASRCS += vfork.S
-CMN_CSRCS += riscv_vfork.c
-endif
-
# Specify our C code within this directory to be included
CHIP_CSRCS = fe310_allocateheap.c fe310_clockconfig.c fe310_gpio.c
CHIP_CSRCS += fe310_irq.c fe310_irq_dispatch.c
diff --git a/arch/risc-v/src/k210/Make.defs b/arch/risc-v/src/k210/Make.defs
index 6c5e10649e..d3e1ec5769 100644
--- a/arch/risc-v/src/k210/Make.defs
+++ b/arch/risc-v/src/k210/Make.defs
@@ -18,48 +18,12 @@
#
############################################################################
+include common/Make.defs
+
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = k210_head.S
-# Specify our general Assembly files
-CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
-
-# Specify C code within the common directory to be included
-CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c
-CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_exception.c
-CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
-CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
-CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
-CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
-CMN_CSRCS += riscv_mdelay.c riscv_idle.c riscv_doirq.c
-CMN_CSRCS += riscv_tcbinfo.c riscv_cpuidlestack.c riscv_getnewintctx.c
-CMN_CSRCS += riscv_misaligned.c riscv_saveusercontext.c
-
-ifeq ($(CONFIG_SMP), y)
-CMN_CSRCS += riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c
-CMN_ASRCS += riscv_mhartid.S
-endif
-
-ifeq ($(CONFIG_SCHED_BACKTRACE),y)
-CMN_CSRCS += riscv_backtrace.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += riscv_checkstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_ASRCS += vfork.S
-CMN_CSRCS += riscv_vfork.c
-endif
-
-ifeq ($(CONFIG_ARCH_FPU),y)
-CMN_ASRCS += riscv_fpu.S
-CMN_CSRCS += riscv_fpucmp.c
-endif
-
# Specify our C code within this directory to be included
CHIP_CSRCS = k210_allocateheap.c k210_clockconfig.c
CHIP_CSRCS += k210_irq.c k210_irq_dispatch.c
@@ -67,9 +31,5 @@ CHIP_CSRCS += k210_lowputc.c k210_serial.c k210_fpioa.c
CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += riscv_task_start.c riscv_pthread_start.c
-CMN_CSRCS += riscv_signal_dispatch.c
-CMN_UASRCS += riscv_signal_handler.S
-
CHIP_CSRCS += k210_userspace.c
endif
diff --git a/arch/risc-v/src/litex/Make.defs b/arch/risc-v/src/litex/Make.defs
index 6c565fb50b..450961a8c9 100644
--- a/arch/risc-v/src/litex/Make.defs
+++ b/arch/risc-v/src/litex/Make.defs
@@ -18,37 +18,12 @@
#
############################################################################
+include common/Make.defs
+
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = litex_head.S
-# Specify our general Assembly files
-CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
-
-# Specify C code within the common directory to be included
-CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_doirq.c riscv_exception.c
-CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
-CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
-CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
-CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
-CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c
riscv_usestack.c
-CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_getnewintctx.c
-CMN_CSRCS += riscv_saveusercontext.c
-
-ifeq ($(CONFIG_SCHED_BACKTRACE),y)
-CMN_CSRCS += riscv_backtrace.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += riscv_checkstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_ASRCS += vfork.S
-CMN_CSRCS += riscv_vfork.c
-endif
-
# Specify our C code within this directory to be included
CHIP_CSRCS = litex_allocateheap.c litex_clockconfig.c
CHIP_CSRCS += litex_irq.c litex_irq_dispatch.c
diff --git a/arch/risc-v/src/mpfs/Make.defs b/arch/risc-v/src/mpfs/Make.defs
index faa7ae14d8..037145a555 100755
--- a/arch/risc-v/src/mpfs/Make.defs
+++ b/arch/risc-v/src/mpfs/Make.defs
@@ -18,9 +18,7 @@
#
############################################################################
-# Specify our general Assembly files
-
-CMN_ASRCS += riscv_vectors.S riscv_exception_common.S riscv_testset.S
+include common/Make.defs
ifeq ($(CONFIG_ARCH_USE_S_MODE),y)
CMN_ASRCS += mpfs_shead.S
@@ -28,44 +26,6 @@ else
CMN_ASRCS += mpfs_head.S
endif
-ifeq ($(CONFIG_BUILD_KERNEL),y)
-STARTUP_OBJS = crt0$(OBJEXT)
-endif
-
-# Specify C code within the common directory to be included
-CMN_CSRCS += riscv_initialize.c riscv_swint.c
-CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_exception.c
-CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
-CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
-CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
-CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
-CMN_CSRCS += riscv_mdelay.c riscv_udelay.c
-CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_getnewintctx.c
-CMN_CSRCS += riscv_doirq.c riscv_mtimer.c
-CMN_CSRCS += riscv_saveusercontext.c
-
-# Specify ASM code within the common directory to be included
-CMN_ASRCS += riscv_mhartid.S
-
-ifeq ($(CONFIG_SCHED_BACKTRACE),y)
-CMN_CSRCS += riscv_backtrace.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += riscv_checkstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_FPU),y)
-CMN_ASRCS += riscv_fpu.S
-CMN_CSRCS += riscv_fpucmp.c
-endif
-
-ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_ASRCS += vfork.S
-CMN_CSRCS += riscv_vfork.c
-endif
-
# Specify our C code within this directory to be included
CHIP_CSRCS = mpfs_allocateheap.c mpfs_clockconfig.c
CHIP_CSRCS += mpfs_irq.c mpfs_irq_dispatch.c
@@ -80,35 +40,12 @@ endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += mpfs_userspace.c
-CMN_UASRCS += riscv_signal_handler.S
endif
ifeq ($(CONFIG_BUILD_KERNEL),y)
CHIP_CSRCS += mpfs_mm_init.c
endif
-ifneq ($(CONFIG_BUILD_FLAT),y)
-CMN_CSRCS += riscv_task_start.c
-CMN_CSRCS += riscv_pthread_start.c
-CMN_CSRCS += riscv_signal_dispatch.c
-endif
-
-ifeq ($(CONFIG_ARCH_USE_MPU),y)
-CMN_CSRCS += riscv_pmp.c
-endif
-
-ifeq ($(CONFIG_ARCH_USE_MMU),y)
-CMN_CSRCS += riscv_mmu.c
-endif
-
-ifeq ($(CONFIG_ARCH_KERNEL_STACK),y)
-CMN_CSRCS += riscv_addrenv_kstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_ADDRENV),y)
-CMN_CSRCS += riscv_addrenv.c riscv_pgalloc.c riscv_addrenv_perms.c
-endif
-
ifeq ($(CONFIG_MM_PGALLOC),y)
CHIP_CSRCS += mpfs_pgalloc.c
endif
diff --git a/arch/risc-v/src/qemu-rv/Make.defs
b/arch/risc-v/src/qemu-rv/Make.defs
index 7fb8ae50e4..3033111cc3 100644
--- a/arch/risc-v/src/qemu-rv/Make.defs
+++ b/arch/risc-v/src/qemu-rv/Make.defs
@@ -18,65 +18,12 @@
#
############################################################################
+include common/Make.defs
+
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = qemu_rv_head.S
-ifeq ($(CONFIG_BUILD_KERNEL),y)
-STARTUP_OBJS = crt0$(OBJEXT)
-endif
-
-# Specify our general Assembly files
-CMN_ASRCS += riscv_vectors.S riscv_exception_common.S
-
-# Specify C code within the common directory to be included
-CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c
-CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
-CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
-CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
-CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
-CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
-CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_cpuidlestack.c
-CMN_CSRCS += riscv_exception.c riscv_getnewintctx.c riscv_doirq.c
-CMN_CSRCS += riscv_saveusercontext.c
-
-ifeq ($(CONFIG_SMP), y)
-CMN_CSRCS += riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c
-CMN_ASRCS += riscv_mhartid.S
-endif
-
-ifeq ($(CONFIG_SCHED_BACKTRACE),y)
-CMN_CSRCS += riscv_backtrace.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += riscv_checkstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_ASRCS += vfork.S
-CMN_CSRCS += riscv_vfork.c
-endif
-
-ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y)
-CMN_CSRCS += riscv_tls.c
-endif
-
-ifeq ($(CONFIG_ARCH_FPU),y)
-CMN_ASRCS += riscv_fpu.S
-CMN_CSRCS += riscv_fpucmp.c
-endif
-
-ifeq ($(CONFIG_ARCH_RV_ISA_A),y)
-CMN_ASRCS += riscv_testset.S
-endif
-
-ifeq ($(CONFIG_RISCV_SEMIHOSTING_HOSTFS),y)
-CMN_ASRCS += riscv_semihost.S
-CMN_CSRCS += riscv_hostfs.c
-endif
-
# Specify our C code within this directory to be included
CHIP_CSRCS = qemu_rv_start.c qemu_rv_irq_dispatch.c qemu_rv_irq.c
CHIP_CSRCS += qemu_rv_timerisr.c qemu_rv_allocateheap.c
@@ -85,28 +32,6 @@ ifeq ($(CONFIG_BUILD_KERNEL),y)
CHIP_CSRCS += qemu_rv_mm_init.c
endif
-ifneq ($(CONFIG_BUILD_FLAT),y)
-CMN_CSRCS += riscv_task_start.c
-CMN_CSRCS += riscv_pthread_start.c
-CMN_CSRCS += riscv_signal_dispatch.c
-endif
-
-ifeq ($(CONFIG_ARCH_USE_MPU),y)
-CMN_CSRCS += riscv_pmp.c
-endif
-
-ifeq ($(CONFIG_ARCH_USE_MMU),y)
-CMN_CSRCS += riscv_mmu.c
-endif
-
-ifeq ($(CONFIG_ARCH_KERNEL_STACK),y)
-CMN_CSRCS += riscv_addrenv_kstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_ADDRENV),y)
-CMN_CSRCS += riscv_addrenv.c riscv_pgalloc.c riscv_addrenv_perms.c
-endif
-
ifeq ($(CONFIG_MM_PGALLOC),y)
CHIP_CSRCS += qemu_rv_pgalloc.c
endif
diff --git a/arch/risc-v/src/rv32m1/Make.defs b/arch/risc-v/src/rv32m1/Make.defs
index 1308c11106..20bf0ed74f 100644
--- a/arch/risc-v/src/rv32m1/Make.defs
+++ b/arch/risc-v/src/rv32m1/Make.defs
@@ -18,36 +18,14 @@
#
############################################################################
+include common/Make.defs
+
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = rv32m1_head.S
# Specify our general Assembly files
-CMN_ASRCS = riscv_vectors.S
-
-# Specify C code within the common directory to be included
-CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_doirq.c riscv_exception.c
-CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
-CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c
riscv_initialstate.c
-CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
-CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
-CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
-CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
-CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_getnewintctx.c
-CMN_CSRCS += riscv_saveusercontext.c
-
-ifeq ($(CONFIG_SCHED_BACKTRACE),y)
-CMN_CSRCS += riscv_backtrace.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += riscv_checkstack.c
-endif
-
-ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_ASRCS += vfork.S
-CMN_CSRCS += riscv_vfork.c
-endif
+CMN_ASRCS := $(filter-out riscv_exception_common.S,$(CMN_ASRCS))
# Specify our C code within this directory to be included
CHIP_CSRCS = rv32m1_allocateheap.c rv32m1_clockconfig.c rv32m1_gpio.c
