xiaoxiang781216 commented on code in PR #6286:
URL: https://github.com/apache/incubator-nuttx/pull/6286#discussion_r876224950
##########
arch/z80/include/irq.h:
##########
@@ -32,4 +32,55 @@
#include <nuttx/irq.h>
#include <arch/chip/irq.h>
+#ifndef __ASSEMBLY__
+# include <stdbool.h>
+# include "chip/switch.h"
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description:
+ * Return true is we are currently executing in the interrupt
+ * handler context.
+ *
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+static inline bool up_interrupt_context(void)
+{
+ return IN_INTERRUPT();
+}
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
Review Comment:
don't need this section if arch doesn't support SMP.
##########
arch/z16/include/irq.h:
##########
@@ -57,6 +62,61 @@ extern "C"
#define EXTERN extern
#endif
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+/* This holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during
+ * interrupt processing.
+ */
+
+EXTERN volatile FAR chipreg_t *g_current_regs;
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description:
+ * Return true is we are currently executing in the interrupt
+ * handler context.
+ *
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+static inline bool up_interrupt_context(void)
+{
+ return g_current_regs != NULL;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
Review Comment:
remove
##########
arch/x86/include/irq.h:
##########
@@ -54,24 +58,70 @@
****************************************************************************/
/****************************************************************************
- * Inline functions
+ * Public Function Prototypes
****************************************************************************/
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
/****************************************************************************
* Public Data
****************************************************************************/
+#ifndef __ASSEMBLY__
+/* This holds a references to the current interrupt level register storage
+ * structure. If is non-NULL only during interrupt processing.
+ */
+
+EXTERN volatile uint32_t *g_current_regs;
+#endif
+
/****************************************************************************
- * Public Function Prototypes
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
Review Comment:
remove
##########
arch/x86_64/include/irq.h:
##########
@@ -74,6 +78,48 @@ extern "C"
#define EXTERN extern
#endif
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
Review Comment:
remove
##########
arch/sim/include/irq.h:
##########
@@ -77,6 +125,7 @@ extern "C"
irqstate_t up_irq_save(void);
void up_irq_restore(irqstate_t flags);
+bool up_interrupt_context(void);
Review Comment:
revert the change if up_interrutp_context isn't linlined
##########
arch/renesas/include/irq.h:
##########
@@ -40,27 +45,70 @@
* Public Types
****************************************************************************/
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
/****************************************************************************
* Public Data
****************************************************************************/
+/* This holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during
+ * interrupt processing.
+ */
+
+EXTERN volatile uint32_t *g_current_regs;
+
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
Review Comment:
remove
##########
arch/hc/include/irq.h:
##########
@@ -55,25 +60,67 @@
* Public Types
****************************************************************************/
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* This holds a references to the current interrupt level register storage
+ * structure. If is non-NULL only during interrupt processing.
+ */
+
+EXTERN volatile uint8_t *g_current_regs;
+
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
- * Public Data
+ * Name: up_interrupt_context
+ *
+ * Description:
+ * Return true is we are currently executing in the interrupt
+ * handler context.
+ *
****************************************************************************/
+static inline bool up_interrupt_context(void)
+{
+ return g_current_regs != NULL;
+}
+
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
Review Comment:
revert
##########
arch/sparc/include/irq.h:
##########
@@ -55,24 +60,66 @@
#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* This holds a references to the current interrupt level register storage
+ * structure. If is non-NULL only during interrupt processing.
+ */
+
+EXTERN volatile uint32_t *g_current_regs;
+
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
- * Public Data
+ * Name: up_interrupt_context
+ *
+ * Description:
+ * Return true is we are currently executing in the interrupt
+ * handler context.
+ *
****************************************************************************/
+static inline bool up_interrupt_context(void)
+{
+ return g_current_regs != NULL;
+}
+
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
Review Comment:
remove
##########
arch/ceva/include/irq.h:
##########
@@ -75,4 +80,80 @@
#define IRQ_VINT25 (IRQ_VINT_FIRST + 25)
#define IRQ_VINT26 (IRQ_VINT_FIRST + 26)
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN uint32_t *volatile g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
+#else
+# define up_cpu_index() (0)
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description:
+ * Return true is we are currently executing in the interrupt
+ * handler context.
+ *
+ ****************************************************************************/
+
+static inline bool up_interrupt_context(void)
+{
+ return CURRENT_REGS != NULL;
Review Comment:
need irqsave here like arm
##########
arch/misoc/include/irq.h:
##########
@@ -56,6 +57,60 @@ extern "C"
#define EXTERN extern
#endif
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* This holds a references to the current interrupt level register storage
+ * structure. If is non-NULL only during interrupt processing.
+ */
+
+EXTERN volatile uint32_t *g_current_regs;
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description:
+ * Return true is we are currently executing in the interrupt
+ * handler context.
+ *
+ ****************************************************************************/
+
+static inline bool up_interrupt_context(void)
+{
+ return g_current_regs != NULL;
+}
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
Review Comment:
revert the change
##########
arch/avr/include/irq.h:
##########
@@ -55,27 +60,73 @@
* Public Types
****************************************************************************/
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
/****************************************************************************
* Public Data
****************************************************************************/
+#ifndef __ASSEMBLY__
+/* This holds a references to the current interrupt level register storage
+ * structure. If is non-NULL only during interrupt processing.
+ */
+
+#ifdef CONFIG_ARCH_FAMILY_AVR32
+EXTERN volatile uint32_t *g_current_regs;
+#else
+EXTERN volatile uint8_t *g_current_regs;
+#endif
+
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
Review Comment:
revert
##########
arch/risc-v/include/irq.h:
##########
@@ -612,18 +661,32 @@ static inline void up_irq_restore(irqstate_t flags)
}
/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_irq_enable
+ * Name: up_interrupt_context
*
* Description:
- * Return the current interrupt state and enable interrupts
+ * Return true is we are currently executing in the interrupt
+ * handler context.
*
****************************************************************************/
-EXTERN irqstate_t up_irq_enable(void);
+static inline bool up_interrupt_context(void)
+{
+#ifdef CONFIG_ARCH_RV64
Review Comment:
why check rv54?
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