xiaoxiang781216 commented on code in PR #6151:
URL: https://github.com/apache/incubator-nuttx/pull/6151#discussion_r859383155
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arch/risc-v/src/common/riscv_mtimer.c:
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@@ -84,7 +84,13 @@ static const struct oneshot_operations_s g_riscv_mtimer_ops =
static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
{
#ifdef CONFIG_ARCH_RV64
- return getreg64(priv->mtime);
+ /* priv->mtime is -1, means this SoC:
+ * 1. does NOT support 64bit write for the mtimer regs,
+ * 2. has NO memory mapped regs which hold the value of mtimer counter,
+ * it could be read from the CSR "time"
+ */
+
+ return (-1 == priv->mtime) ? READ_CSR(time) : getreg64(priv->mtime);
Review Comment:
remove () around "-1 == priv->mtime"?
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