xiaoxiang781216 commented on a change in pull request #5782:
URL: https://github.com/apache/incubator-nuttx/pull/5782#discussion_r837389096
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File path: arch/risc-v/src/common/supervisor/riscv_sbi.c
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@@ -41,7 +47,11 @@
void riscv_sbi_ack_timer(void)
{
+#ifdef CONFIG_NUTTSBI
+ riscv_mcall_ack_timer();
Review comment:
> I think I might be wrong on this. This detail was VERY well hidden in
the RISC-V privileged spec. But according to this:
[riscv-software-src/riscv-pk#184](https://github.com/riscv-software-src/riscv-pk/issues/184)
>
Good finding.
> mtime apparently is accessible to the supervisor, via CSR called "time"
which apparently, implicitly equals mtime, or at least can be used as a seed
for calculating values for sbi_set_timer(abs_time). This detail was not at all
apparent to me and I won't believe it works until I have tried.
>
I think we can add a general macro to mode.h, so the same macro can be used
with in S-mode and M-mode.
> The reason I'm thoroughly confused, is because the mtime/mtimecmp
registers are not really CSRs accessible with the csr instructions. They are
memory mapped registers that reside in the CLINT memory space, and are accessed
via the normal ld/sd instructions, which reference memory (not registers).
>
From my previous experience with IC designer, the source of timer CSR may
come from(connect to) the external timer.
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