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commit d21d02c65d84d240d42f419d22efc74500e78cb1
Author: Abdelatif Guettouche <abdelatif.guettou...@espressif.com>
AuthorDate: Mon Mar 14 11:14:09 2022 +0100
xtensa_panic.S: Save exception cause and vaddr into the user frame.
This area is what's passed later to assert and be used to dump the
state.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettou...@espressif.com>
---
arch/xtensa/src/common/xtensa_panic.S | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/xtensa/src/common/xtensa_panic.S
b/arch/xtensa/src/common/xtensa_panic.S
index e6eaac1..f5ebd53 100644
--- a/arch/xtensa/src/common/xtensa_panic.S
+++ b/arch/xtensa/src/common/xtensa_panic.S
@@ -128,6 +128,13 @@ _xtensa_panic:
call0 _xtensa_context_save /* Save full register
state */
+ /* Save exception cause and vaddr into the user frame */
+
+ rsr a0, EXCCAUSE
+ s32i a0, sp, (4 * REG_EXCCAUSE)
+ rsr a0, EXCVADDR
+ s32i a0, sp, (4 * REG_EXCVADDR)
+
/* Dispatch the sycall as with other interrupts. */
mov a12, sp
/* a12 = address of register save area */
@@ -138,13 +145,6 @@ _xtensa_panic:
setintstack a13 a14
#endif
- /* Save exc cause and vaddr into exception frame */
-
- rsr a0, EXCCAUSE
- s32i a0, sp, (4 * REG_EXCCAUSE)
- rsr a0, EXCVADDR
- s32i a0, sp, (4 * REG_EXCVADDR)
-
/* Set up PS for C, re-enable hi-pri interrupts, and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
