[incubator-nuttx] 01/02: xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled

[xiaoxiang]

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commit a4db4031c9c804a771c97ce95edf2ce2a1181d9a
Author: Gustavo Henrique Nihei <gustavo.ni...@espressif.com>
AuthorDate: Fri Mar 11 09:30:52 2022 -0300

    xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled
    
    Signed-off-by: Gustavo Henrique Nihei <gustavo.ni...@espressif.com>
---
 arch/xtensa/src/esp32s3/esp32s3_tickless.c | 3 +++
 arch/xtensa/src/esp32s3/esp32s3_timerisr.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/arch/xtensa/src/esp32s3/esp32s3_tickless.c 
b/arch/xtensa/src/esp32s3/esp32s3_tickless.c
index 7e188b3..e379c48 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_tickless.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_tickless.c
@@ -479,6 +479,9 @@ void up_timer_initialize(void)
   /* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
 
   modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
+#ifdef CONFIG_SMP
+  modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN);
+#endif
 }
 
 #endif /* CONFIG_SCHED_TICKLESS */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c 
b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
index 30896f0..e2d4b23 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
@@ -130,6 +130,9 @@ void up_timer_initialize(void)
   /* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
 
   modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
+#ifdef CONFIG_SMP
+  modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN);
+#endif
 
   /* Enable interrupt */