pkarashchenko commented on a change in pull request #5686: URL: https://github.com/apache/incubator-nuttx/pull/5686#discussion_r822075319
########## File path: arch/xtensa/src/esp32s3/esp32s3_psram.c ########## @@ -0,0 +1,559 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_psram.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <stdint.h> +#include <stddef.h> +#include <errno.h> +#include <debug.h> + +#include "esp32s3_gpio.h" +#include "esp32s3_psram.h" + +#include "rom/esp32s3_spiflash.h" +#include "rom/esp32s3_opi_flash.h" +#include "hardware/esp32s3_spi_mem_reg.h" +#include "hardware/esp32s3_iomux.h" +#include "hardware/esp32s3_gpio_sigmap.h" + +/* EFUSE */ + +#define ESP_ROM_EFUSE_FLASH_DEFAULT_SPI (0) + +extern uint32_t esp_rom_efuse_get_flash_gpio_info(void); +extern uint32_t esp_rom_efuse_get_flash_wp_gpio(void); + +/* Commands for PSRAM chip */ + +#define PSRAM_READ 0x03 +#define PSRAM_FAST_READ 0x0B +#define PSRAM_FAST_READ_QUAD 0xEB +#define PSRAM_WRITE 0x02 +#define PSRAM_QUAD_WRITE 0x38 +#define PSRAM_ENTER_QMODE 0x35 +#define PSRAM_EXIT_QMODE 0xF5 +#define PSRAM_RESET_EN 0x66 +#define PSRAM_RESET 0x99 +#define PSRAM_SET_BURST_LEN 0xC0 +#define PSRAM_DEVICE_ID 0x9F + +#define PSRAM_FAST_READ_DUMMY 4 +#define PSRAM_FAST_READ_QUAD_DUMMY 6 + +/* ID */ + +#define PSRAM_ID_KGD_M 0xff +#define PSRAM_ID_KGD_S 8 +#define PSRAM_ID_KGD 0x5d +#define PSRAM_ID_EID_M 0xff +#define PSRAM_ID_EID_S 16 + +/* Use the [7:5](bit7~bit5) of EID to distinguish the psram size: + * + * BIT7 | BIT6 | BIT5 | SIZE(MBIT) + * ------------------------------------- + * 0 | 0 | 0 | 16 + * 0 | 0 | 1 | 32 + * 0 | 1 | 0 | 64 + */ + +#define PSRAM_EID_SIZE_M 0x07 +#define PSRAM_EID_SIZE_S 5 + +#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) +#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) +#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M) +#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) + +#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26) + +/* IO-pins for PSRAM. + * WARNING: PSRAM shares all but the CS and CLK pins with the flash, so + * these defines hardcode the flash pins as well, making this code + * incompatible with either a setup that has the flash on non-standard + * pins or ESP32s with built-in flash. + */ + +#define FLASH_CLK_IO SPI_CLK_GPIO_NUM +#define FLASH_CS_IO SPI_CS0_GPIO_NUM + +/* PSRAM clock and cs IO should be configured based on hardware design. */ + +#define PSRAM_CLK_IO CONFIG_ESP32S3_DEFAULT_PSRAM_CLK_IO /* Default value is 30 */ +#define PSRAM_CS_IO CONFIG_ESP32S3_DEFAULT_PSRAM_CS_IO /* Default value is 26 */ +#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM +#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM +#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM +#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM + +#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M +#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M + +#define SPI1_NUM 1 +#define SPI0_NUM 0 + +typedef enum +{ + PSRAM_CMD_QPI, + PSRAM_CMD_SPI, +} psram_cmd_mode_e; + +uint32_t g_psram_id; +uint32_t g_psram_size; /* physical psram size in bytes */ + +static void config_psram_spi_phases(void); +extern void esp_rom_spi_set_op_mode(int spi_num, + esp_rom_spiflash_read_mode_t mode); + +static uint8_t g_psram_cs_io = UINT8_MAX; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +uint8_t psram_get_cs_io(void) +{ + return g_psram_cs_io; +} + +static void psram_set_op_mode(int spi_num, int mode) +{ + if (mode == PSRAM_CMD_QPI) + { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE); + SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); + } + else if (mode == PSRAM_CMD_SPI) + { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE); + } +} + +static void _psram_exec_cmd(int spi_num, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, uint8_t *mosi_data, + int mosi_bit_len, uint8_t *miso_data, + int miso_bit_len) +{ + esp_rom_spi_cmd_t conf; + uint32_t _addr = addr; + conf.addr = &_addr; + conf.addr_bit_len = addr_bit_len; + conf.cmd = cmd; + conf.cmd_bit_len = cmd_bit_len; + conf.dummy_bit_len = dummy_bits; /* There is a hw approach on chip723 */ + conf.tx_data = (uint32_t *) mosi_data; + conf.tx_data_bit_len = mosi_bit_len; + conf.rx_data = (uint32_t *) miso_data; + conf.rx_data_bit_len = miso_bit_len; + esp_rom_spi_cmd_config(spi_num, &conf); +} + +void psram_exec_cmd(int spi_num, int mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, uint8_t *mosi_data, + int mosi_bit_len, uint8_t *miso_data, + int miso_bit_len, uint32_t cs_mask, + bool is_write_erase_operation) +{ + uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); + uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); + uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num)); + uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); + + psram_set_op_mode(spi_num, mode); + _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, + addr_bit_len, dummy_bits, mosi_data, + mosi_bit_len, miso_data, miso_bit_len); + + esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, + cs_mask, is_write_erase_operation); + + WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); + WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1); + WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2); + WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl); +} + +/* exit QPI mode(set back to SPI mode) */ + +static void psram_disable_qio_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_QPI, + PSRAM_EXIT_QMODE, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/* switch psram burst length(32 bytes or 1024 bytes) + * datasheet says it should be 1024 bytes by default + */ + +static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_e mode) +{ + psram_exec_cmd(spi_num, mode, + PSRAM_SET_BURST_LEN, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/* send reset command to psram, in spi mode */ + +static void psram_reset_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET_EN, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ + + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int psram_enable_wrap(uint32_t wrap_size) +{ + static uint32_t current_wrap_size; + + if (current_wrap_size == wrap_size) + { + return OK; + } + + switch (wrap_size) + { + case 32: + case 0: + psram_set_wrap_burst_length(1, PSRAM_CMD_QPI); + current_wrap_size = wrap_size; + return OK; + case 16: + case 64: + default: + return -EFAULT; + } +} + +bool psram_support_wrap_size(uint32_t wrap_size) +{ + switch (wrap_size) + { + case 0: + case 32: + return true; + case 16: + case 64: + default: + return false; + } +} + +/* Read ID operation only supports SPI CMD and mode, should issue + * `psram_disable_qio_mode` before calling this + */ + +static void psram_read_id(int spi_num, uint32_t *dev_id) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_DEVICE_ID, 8, /* command and command bit len */ + 0, 24, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + (uint8_t *) dev_id, 24, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/* enter QPI mode */ + +static void psram_enable_qio_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_ENTER_QMODE, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +static void psram_set_cs_timing(void) +{ + /* SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time + * registers for PSRAM, so we only need to set SPI0 related registers here + */ + + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), + SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 0, + SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), + SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, + SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), + SPI_MEM_SPI_SMEM_CS_HOLD_M | \ Review comment: ```suggestion SPI_MEM_SPI_SMEM_CS_HOLD_M | ``` -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
