davids5 opened a new pull request #2943:
URL: https://github.com/apache/incubator-nuttx/pull/2943
## Summary
On The STM32F7 the RCC LSE code was hanging on waiting for OSC ready ~15% of
a a board run. The root cause was determined to be the the variation in crystal
response to the drive.
On The STM32H7 the RCC LSE code was hanging on waiting for OSC ready on Rev
V silicon.
This PR fixes these issues.
When eanbled STM32x7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY will cycle
through the correct* values from low to high. To avoid damaging the crystal.
We want to use the lowest setting that gets the OSC running. See app note AN2867
On the H7 Rev V slicon
*It will take into account the rev of the silicon and use the correct
code points to achieve the drive
strength. See Eratta ES0392 Rev 7 2.2.14 LSE oscillator driving
capability selection bits are swapped.
## Impact
None if the Knob is not set.
It will start the LSE or time out. In the latter case higher level SW can
determine the RTC is not running, and can report it. Before the code would hang
so early in boot, that a system would appear to be bricked.
## Testing
15 F7 boards were tested, All Bards that failed to start the LSE on master
work with the F7 commit. The values set were determined to be medium-low.
H7 - boards with Rev V silicon that failed to start the LSE on master work
with the H7 commit. The values set were determined to be medium-low.
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