acassis commented on a change in pull request #2721: URL: https://github.com/apache/incubator-nuttx/pull/2721#discussion_r561272506
########## File path: arch/xtensa/src/esp32/esp32_efuse.c ########## @@ -0,0 +1,486 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_efuse_utils.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <debug.h> +#include <errno.h> +#include <assert.h> +#include <string.h> +#include <nuttx/efuse/efuse.h> + +#include "xtensa.h" +#include "esp32_efuse.h" +#include "esp32_clockconfig.h" +#include "hardware/efuse_reg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EFUSE_CONF_WRITE 0x5a5a /* eFuse_pgm_op_ena, force no rd/wr dis. */ +#define EFUSE_CONF_READ 0x5aa5 /* eFuse_read_op_ena, release force. */ +#define EFUSE_CMD_PGM 0x02 /* Command to program. */ +#define EFUSE_CMD_READ 0x01 /* Command to read. */ + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + +uint32_t g_start_efuse_rdreg[4] = +{ + EFUSE_BLK0_RDATA0_REG, + EFUSE_BLK1_RDATA0_REG, + EFUSE_BLK2_RDATA0_REG, + EFUSE_BLK3_RDATA0_REG +}; + +uint32_t g_start_efuse_wrreg[4] = +{ + EFUSE_BLK0_WDATA0_REG, + EFUSE_BLK1_WDATA0_REG, + EFUSE_BLK2_WDATA0_REG, + EFUSE_BLK3_WDATA0_REG +}; + +void esp_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int esp_efuse_set_timing(void) +{ + uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000; + uint32_t clk_sel0; + uint32_t clk_sel1; + uint32_t dac_clk_div; + + if (apb_freq_mhz <= 26) + { + clk_sel0 = 250; + clk_sel1 = 255; + dac_clk_div = 52; + } + else + { + if (apb_freq_mhz <= 40) + { + clk_sel0 = 160; + clk_sel1 = 255; + dac_clk_div = 80; + } + else + { + clk_sel0 = 80; + clk_sel1 = 128; + dac_clk_div = 100; + } + } + + REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div); + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0); + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1); + return OK; +} + +/* efuse read operation: copies data from physical efuses to efuse read + * registers. + */ + +void esp_efuse_clear_program_regs(void) +{ + putreg32(EFUSE_CONF_READ, EFUSE_CONF_REG); +} + +/* Burn values written to the efuse write registers */ + +void esp_efuse_burn_efuses(void) Review comment: this one is used by the efuse_lowerhalf, cannot be static ########## File path: arch/xtensa/src/esp32/esp32_efuse.c ########## @@ -0,0 +1,486 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_efuse_utils.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <debug.h> +#include <errno.h> +#include <assert.h> +#include <string.h> +#include <nuttx/efuse/efuse.h> + +#include "xtensa.h" +#include "esp32_efuse.h" +#include "esp32_clockconfig.h" +#include "hardware/efuse_reg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EFUSE_CONF_WRITE 0x5a5a /* eFuse_pgm_op_ena, force no rd/wr dis. */ +#define EFUSE_CONF_READ 0x5aa5 /* eFuse_read_op_ena, release force. */ +#define EFUSE_CMD_PGM 0x02 /* Command to program. */ +#define EFUSE_CMD_READ 0x01 /* Command to read. */ + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + +uint32_t g_start_efuse_rdreg[4] = +{ + EFUSE_BLK0_RDATA0_REG, + EFUSE_BLK1_RDATA0_REG, + EFUSE_BLK2_RDATA0_REG, + EFUSE_BLK3_RDATA0_REG +}; + +uint32_t g_start_efuse_wrreg[4] = +{ + EFUSE_BLK0_WDATA0_REG, + EFUSE_BLK1_WDATA0_REG, + EFUSE_BLK2_WDATA0_REG, + EFUSE_BLK3_WDATA0_REG +}; + +void esp_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int esp_efuse_set_timing(void) +{ + uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000; + uint32_t clk_sel0; + uint32_t clk_sel1; + uint32_t dac_clk_div; + + if (apb_freq_mhz <= 26) + { + clk_sel0 = 250; + clk_sel1 = 255; + dac_clk_div = 52; + } + else + { + if (apb_freq_mhz <= 40) + { + clk_sel0 = 160; + clk_sel1 = 255; + dac_clk_div = 80; + } + else + { + clk_sel0 = 80; + clk_sel1 = 128; + dac_clk_div = 100; + } + } + + REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div); + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0); + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1); + return OK; +} + +/* efuse read operation: copies data from physical efuses to efuse read + * registers. + */ + +void esp_efuse_clear_program_regs(void) +{ + putreg32(EFUSE_CONF_READ, EFUSE_CONF_REG); +} + +/* Burn values written to the efuse write registers */ + +void esp_efuse_burn_efuses(void) +{ + esp_efuse_set_timing(); + + /* Permanently update values written to the efuse write registers */ + + putreg32(EFUSE_CONF_WRITE, EFUSE_CONF_REG); + putreg32(EFUSE_CMD_PGM, EFUSE_CMD_REG); + + while (getreg32(EFUSE_CMD_REG) != 0) + { + }; + + putreg32(EFUSE_CONF_READ, EFUSE_CONF_REG); + putreg32(EFUSE_CMD_READ, EFUSE_CMD_REG); + + while (getreg32(EFUSE_CMD_REG) != 0) + { + }; +} + +/* return mask with required the number of ones with shift */ + +static uint32_t get_mask(uint32_t bit_count, uint32_t shift) +{ + uint32_t mask; + + if (bit_count != 32) + { + mask = (1 << bit_count) - 1; + } + else + { + mask = 0xffffffff; + } + + return mask << shift; +} + +/* return the register number in the array + * return -1 if all registers for field was selected + */ + +static int get_reg_num(int bit_offset, int bit_count, int i_reg) +{ + uint32_t bit_start = (bit_offset % 256); + int num_reg = i_reg + bit_start / 32; + + if (num_reg > (bit_start + bit_count - 1) / 32) + { + return -1; + } + + return num_reg; +} + +/* returns the starting bit number in the register */ + +static int get_starting_bit_num_in_reg(int bit_start, int i_reg) +{ + return (i_reg == 0) ? bit_start % 32 : 0; +} + +/* Returns the number of bits in the register */ + +static int get_count_bits_in_reg(int bit_offset, int bit_count, int i_reg) +{ + int ret_count = 0; + int num_reg = 0; + int bit_start = (bit_offset % 256); + int last_used_bit = (bit_start + bit_count - 1); + + for (int num_bit = bit_start; num_bit <= last_used_bit; ++num_bit) + { + ++ret_count; + if ((((num_bit + 1) % 32) == 0) || (num_bit == last_used_bit)) + { + if (i_reg == num_reg++) + { + return ret_count; + } + + ret_count = 0; + } + } + + return 0; +} + +/* get the length of the field in bits */ + +int esp_efuse_get_field_size(const efuse_desc_t *field[]) +{ + int bits_counter = 0; + + if (field != NULL) + { + int i = 0; + + while (field[i] != NULL) + { + bits_counter += field[i]->bit_count; + ++i; + } + } + + return bits_counter; +} + +/* check range of bits for any coding scheme */ + +static bool check_range_of_bits(int offset_in_bits, int size_bits) +{ + int blk_offset = offset_in_bits % 256; + int max_num_bit = blk_offset + size_bits; + + if (max_num_bit > 256) + { + return false; + } + + return true; +} + +/* Returns the number of array elements for placing these bits in an array + * with the length of each element equal to size_of_base. + */ + +int esp_efuse_get_number_of_items(int bits, int size_of_base) Review comment: Added, thank you! ########## File path: arch/xtensa/src/esp32/esp32_efuse_utils.c ########## @@ -0,0 +1,484 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_efuse_utils.c Review comment: Good catch, this file is reminiscent from old efuse driver that was integrated months ago ########## File path: include/nuttx/efuse/esp_efuse_table.h ########## @@ -0,0 +1,69 @@ +/**************************************************************************** + * include/nuttx/efuse/esp_efuse_table.h Review comment: I don't think so, this header file is exported to applications and this is just an export mirror of the arch/xtensa/src/esp32/esp32_efuse_table.c ---------------------------------------------------------------- This is an automated message from the Apache Git Service. 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