v01d commented on a change in pull request #2566: URL: https://github.com/apache/incubator-nuttx/pull/2566#discussion_r546185504
########## File path: arch/risc-v/src/bl602/hardware/bl602_common.h ########## @@ -0,0 +1,231 @@ +/**************************************************************************** + * arch/risc-v/src/bl602/hardware/bl602_common.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H +#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <stdint.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BL602_FLASH_XIP_BASE 0x23000000 +#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000 +#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000 +#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000 +#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024) + +#define BL602_WRAM_BASE 0x42020000 +#define BL602_WRAM_END (0x42020000 + 176 * 1024) +#define BL602_WRAM_REMAP0_BASE 0x22020000 +#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024) +#define BL602_WRAM_REMAP1_BASE 0x32020000 +#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024) +#define BL602_WRAM_REMAP2_BASE 0x52020000 +#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024) + +#define BL602_TCM_BASE 0x22008000 +#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP0_BASE 0x32008000 +#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP1_BASE 0x42008000 +#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP2_BASE 0x52008000 +#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024) + +/* BL602 peripherals base address */ + +#define GLB_BASE ((uint32_t)0x40000000) +#define RF_BASE ((uint32_t)0x40001000) + +/* AUX module base address */ + +#define GPIP_BASE ((uint32_t)0x40002000) + +/* Security Debug module base address */ + +#define SEC_DBG_BASE ((uint32_t)0x40003000) + +/* Security Engine module base address */ + +#define SEC_ENG_BASE ((uint32_t)0x40004000) + +/* Trustzone control security base address */ + +#define TZC_SEC_BASE ((uint32_t)0x40005000) + +/* Trustzone control none-security base address */ + +#define TZC_NSEC_BASE ((uint32_t)0x40006000) +#define EF_DATA_BASE ((uint32_t)0x40007000) +#define EF_CTRL_BASE ((uint32_t)0x40007000) +#define CCI_BASE ((uint32_t)0x40008000) + +/* L1 cache config base address */ + +#define L1C_BASE ((uint32_t)0x40009000) +#define UART0_BASE ((uint32_t)0x4000A000) +#define UART1_BASE ((uint32_t)0x4000A100) +#define SPI_BASE ((uint32_t)0x4000A200) +#define I2C_BASE ((uint32_t)0x4000A300) +#define PWM_BASE ((uint32_t)0x4000A400) +#define TIMER_BASE ((uint32_t)0x4000A500) +#define IR_BASE ((uint32_t)0x4000A600) +#define SF_CTRL_BASE ((uint32_t)0x4000B000) +#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700) +#define DMA_BASE ((uint32_t)0x4000C000) +#define SDU_BASE ((uint32_t)0x4000D000) + +/* Power down sleep module base address */ + +#define PDS_BASE ((uint32_t)0x4000E000) + +/* Hibernate module base address */ + +#define HBN_BASE ((uint32_t)0x4000F000) + +/* Always on module base address */ + +#define AON_BASE ((uint32_t)0x4000F000) +#define HBN_RAM_BASE ((uint32_t)0x40010000) + +#define BL_RD_WORD(addr) (*((volatile uint32_t *)(addr))) +#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(addr)) = (val)) +#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(addr))) +#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(addr)) = (val)) +#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(addr))) +#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(addr)) = (val)) +#define BL_RDWD_FRM_BYTEP(p) \ + ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) +#define BL_WRWD_TO_BYTEP(p, val) \ + { \ + p[0] = val & 0xff; \ + p[1] = (val >> 8) & 0xff; \ + p[2] = (val >> 16) & 0xff; \ + p[3] = (val >> 24) & 0xff; \ + } +/** + * @brief Register access macro + */ +#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) +#define BL_WR_REG16(addr, regname, val) \ + BL_WR_SHORT(addr + regname##_OFFSET, val) +#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) +#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) Review comment: registers should already be defined as from a base and an offset into a macro, there shouldn't be a macro to do this as a function ---------------------------------------------------------------- This is an automated message from the Apache Git Service. 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